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MSP430F135IRTDR Datasheet(PDF) 26 Page - Texas Instruments

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Part No. MSP430F135IRTDR
Description  MIXED SIGNAL MICROCONTROLLER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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MSP430F135IRTDR Datasheet(HTML) 26 Page - Texas Instruments

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MSP430x13x, MSP430x14x, MSP430x14x1
MIXED SIGNAL MICROCONTROLLER
SLAS272F − JULY 2000 − REVISED JUNE 2004
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT+
Positive-going input threshold voltage
VCC = 2.2 V
1.1
1.5
V
VIT+
Positive-going input threshold voltage
VCC = 3 V
1.5
1.9
V
VIT−
Negative-going input threshold voltage
VCC = 2.2 V
0.4
0.9
V
VIT−
Negative-going input threshold voltage
VCC = 3 V
0.90
1.3
V
Vhys
Input voltage hysteresis (VIT+ − VIT−)
VCC = 2.2 V
0.3
1.1
V
Vhys
Input voltage hysteresis (VIT+ − VIT−)
VCC = 3 V
0.5
1
V
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
Low-level input voltage
VCC = 2.2 V / 3 V
VSS
VSS+0.6
V
VIH
High-level input voltage
VCC = 2.2 V / 3 V
0.8
×VCC
VCC
V
inputs Px.x, TAx, TBx
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Port P1, P2: P1.x to P2.x, external trigger signal
2.2 V/3 V
1.5
cycle
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
2.2 V
62
ns
t(int)
External interrupt timing
for the interrupt flag, (see Note 1)
3 V
50
ns
Timer_A, Timer_B capture
TA0, TA1, TA2
2.2 V
62
t(cap)
Timer_A, Timer_B capture
timing
TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see
Note 2)
3 V
50
ns
f(TAext)
Timer_A, Timer_B clock
frequency externally applied
TACLK, TBCLK, INCLK: t(H) = t(L)
2.2 V
8
MHz
f(TBext)
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t(H) = t(L)
3 V
10
MHz
f(TAint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
2.2 V
8
MHz
f(TBint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
3 V
10
MHz
NOTES:
1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. Seven capture/compare registers in ’x14x(1) and three capture/compare registers in ’x13x.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ilkg(P1.x)
Leakage
Port P1
V(P1.x) (see Note 2)
±50
Ilkg(P2.x)
Leakage
current (see
Note 1)
Port P2
V(P2.3) V(P2.4) (see Note 2)
VCC = 2.2 V/3 V
±50
nA
Ilkg(P6.x)
current (see
Note 1)
Port P6
V(P6.x) (see Note 2)
VCC = 2.2 V/3 V
±50
nA
NOTES:
1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.


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