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MSP430F135IRTDR Datasheet(PDF) 35 Page - Texas Instruments

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Part No. MSP430F135IRTDR
Description  MIXED SIGNAL MICROCONTROLLER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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MSP430F135IRTDR Datasheet(HTML) 35 Page - Texas Instruments

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MSP430x13x, MSP430x14x, MSP430x14x1
MIXED SIGNAL MICROCONTROLLER
SLAS272F − JULY 2000 − REVISED JUNE 2004
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VREF+
Positive built-in reference
REF2_5V = 1 for 2.5 V
IVREF+ ≤ IVREF+max
3 V
2.4
2.5
2.6
V
VREF+
Positive built-in reference
voltage output
REF2_5V = 0 for 1.5 V
IVREF+ ≤ IVREF+max
2.2 V/3 V
1.44
1.5
1.56
V
AVCC minimum voltage,
REF2_5V = 0, IVREF+ ≤ 1mA
2.2
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
REF2_5V = 1, IVREF+ ≤ 0.5mA
VREF+ + 0.15
V
AVCC(min)
Positive built-in reference
active
REF2_5V = 1, IVREF+ ≤ 1mA
VREF+ + 0.15
V
IVREF+
Load current out of VREF+
2.2 V
0.01
−0.5
mA
IVREF+
Load current out of VREF+
terminal
3 V
−1
mA
IVREF+ = 500 µA +/− 100 µA
Analog input voltage ~0.75 V;
2.2 V
±2
LSB
IL(VREF)+ †
Load-current regulation
VREF+
Analog input voltage ~0.75 V;
REF2_5V = 0
3 V
±2
LSB
IL(VREF)+ †
Load-current regulation
VREF+ terminal
IVREF+ = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
REF2_5V = 1
3 V
±2
LSB
IDL(VREF) +‡
Load current regulation
IVREF+ =100 µA → 900 µA,
CVREF+=5 µF, ax ~0.5 x VREF+
3 V
20
ns
IDL(VREF) +‡
Load current regulation
VREF+ terminal
VREF+
CVREF+=5 µF, ax ~0.5 x VREF+
Error of conversion result
≤ 1 LSB
3 V
20
ns
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA
≤ IVREF+ ≤ IVREF+max
2.2 V/3 V
5
10
µF
TREF+†
Temperature coefficient of
built-in reference
IVREF+ is a constant in the range of
0 mA
≤ IVREF+ ≤ 1 mA
2.2 V/3 V
±100 ppm/°C
tREFON†
Settle time of internal
reference voltage (see
Figure 13 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
17
ms
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES:
1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 µF tantalum and 100 nF ceramic.
NOTES:
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
1
µF
0
1 ms
10 ms
100 ms
tREFON
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF
100
µF
10
µF
Figure 13. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+


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