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SC1103CS Datasheet(PDF) 5 Page - Semtech Corporation |
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SC1103CS Datasheet(HTML) 5 Page - Semtech Corporation |
5 / 8 page SC1103 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA VOLTAGE MODE PWM CONTROLLER PRELIMINARY - February 29, 2000 5 LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1103 PWM controller. High currents switching at 200kHz are pre- sent in the application and their effect on ground plane voltage differentials must be understood and mini- mized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to con- strain ground currents to particular areas, for example the input capacitor and bottom Schottky ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Schottky (D1) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will reduce EMI, lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and mini- mize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, D1 and the output inductor should be a wide trace or cop- per region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connec- tion between the output inductor and the sense resis- tor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnec- essary impedance will reduce efficiency. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1103 is best placed over an isolated ground plane area. GND and PGND should be returned to this isolated ground. This isolated ground area should be connected to the main ground by a trace that runs from the GND pin to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, D1 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q1, D1 loop. 6) Vcc for the SC1103 should be supplied from the VIN supply through a 10 Ω resistor, the Vcc pin should Vout 12V 4uH 5mOhm + Cout + Cin 10 0.1uF 2.32k 1.00k Q1 0.1uF 24V IN Heavy lines indicate high current paths. D1 SC1103CS GND 8 VCC 1 CS(-) 2 CS(+) 3 PGND 4 DH 5 BST 6 FB 7 Rb Ra Fig. 7 Layout diagram for the SC1103 |
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