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MSP430F4132IPMR Datasheet(PDF) 12 Page - Texas Instruments |
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MSP430F4132IPMR Datasheet(HTML) 12 Page - Texas Instruments |
12 / 82 page MSP430F41x2 MIXED SIGNAL MICROCONTROLLER SLAS648E -- APRIL 2009 -- REVISED MARCH 2011 12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU goes into LPM4 immediately after power-up. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-Up External Reset Watchdog Flash Memory PC Out--of--Range (see Note 4) PORIFG RSTIFG WDTIFG KEYV (see Note 1) Reset 0xFFFE 15, highest NMI Oscillator Fault Flash Memory Access Violation NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 3) ACCVIFG (see Notes 1, 2, and 4) (Non)maskable (Non)maskable (Non)maskable 0xFFFC 14 Timer_A5 TA1CCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13 Timer_A5 TA1CCR1 to TACCR4 CCIFGs, and TAIFG (see Notes 1 and 2) Maskable 0xFFF8 12 Comparator_A+ CAIFG Maskable 0xFFF6 11 Watchdog Timer+ WDTIFG Maskable 0xFFF4 10 USCI_A0/B0 Receive UCA0RXIFG (see Note 1), UCB0RXIFG (SPI mode), or UCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG (I2C mode) (see Note 1) Maskable 0xFFF2 9 USCI_A0/B0 Transmit UCA0TXIFG (see Note 1), UCB0TXIFG (SPI mode), or UCB0RXIFG and UCB0TXIFG (I2C mode) (see Note 1) Maskable 0xFFF0 8 ADC10 ADC10IFG (see Note 2) Maskable 0xFFEE 7 Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6 Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2, TAIFG (see Notes 1 and 2) Maskable 0xFFEA 5 I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4 0xFFE6 3 0xFFE4 2 I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1 Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. 4. Access and key violations, KEYV and ACCVIFG. |
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