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LCDA05 Datasheet(PDF) 5 Page - Semtech Corporation

Part No. LCDA05
Description  Low Capacitance TVS Diode Array For High-Speed Data Interfaces 
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Maker  SEMTECH [Semtech Corporation]
Homepage  http://www.semtech.com
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LCDA05 Datasheet(HTML) 5 Page - Semtech Corporation

   
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ã 2000 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
LCDA05 THRU LCDA24
Applications Information
Device Connection for Protection of Two High-Speed
Data Lines
The LCDAxx is designed to protect up to two high-speed
data lines. The LCDAxx utilizes a low capacitance
compensation diode in series with, but in opposite
polarity to a TVS diode in each line. The resulting
capacitance is less than 5pF per line. Each line will
only suppress transient events in one polarity. There-
fore, to achieve protection in both positive and nega-
tive polarity, a second TVS/rectifier pair is connected in
anti-parallel to the first. Pins 1, 2, 7, and 8 are used to
protect one data line. Pins 3, 4, 5, and 6 are used to
protect the second data line.
The device is connected as follows:
l
Pins 1 & 2 are tied together and pins 7 & 8 are tied
together providing the protection circuit for one I/O
line. Pins 3 & 4 are tied together and pins 5 & 6
are tied together providing the protection circuit for
the second I/O line. Since the device is electrically
symmetrical, either side of the connected pairs
may be used to protect the lines. The other side of
the pair is used to make the ground connection.
The ground connections should be made directly to
the ground plane for best results. The path length
is kept as short as possible to reduce the effects
of parasitic inductance in the board traces.
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
l
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
l
Minimize the path length between the TVS and the
protected line.
l
Minimize all conductive loops including power and
ground loops.
l
The ESD transient return path to ground should be
kept as short as possible.
l
Never run critical signals near board edges.
l
Use ground planes whenever possible.
I/O 1
I/O 2
I/O 1
I/O 2
1
2
3
45
6
7
8
1
2
3
45
6
7
8
Line 1
In/Out
Line 1
Ground
Line 2
In/Out
Line 2
Ground
From Connector
To Protected
Device
1
2
3
45
6
7
8
Line 1
In/Out
Ground
Line 2
In/Out
From Connector
To Protected
Device
Connection Options
I/O Line Protection
LCDA Connection Diagram


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