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PCF8582C-2T-03 Datasheet(PDF) 11 Page - NXP Semiconductors

Part No. PCF8582C-2T-03
Description  256 x 8-bit CMOS EEPROM with I2C-bus interface
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF8582C-2T-03 Datasheet(HTML) 11 Page - NXP Semiconductors

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Philips Semiconductors
PCF8582C-2
256
× 8-bit CMOS EEPROM with I2C-bus interface
Product data
Rev. 04 — 25 October 2004
11 of 21
9397 750 14222
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. I2C-bus characteristics
[1]
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
SDA input/output (pin 5)
VIL
LOW level input voltage
−0.8
-
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD
-
+6.5
V
VOL
LOW level output voltage
IOL = 3 mA; VDD(min)
-
-
0.4
V
ILO
output leakage current
VOH =VDD
--1
µA
Ci
input capacitance
VI =VSS
--7
pF
Data retention time
tS
data retention time
Tamb =55 °C10
−−
years
Table 7:
Characteristics…continued
VDD = 2.5 to 6.0 V; VSS =0V; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 8:
I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
clock frequency
0
100
kHz
tBUF
bus free time between a STOP and
START condition
4.7
−µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
−µs
tLOW
LOW level clock period
4.7
−µs
tHIGH
HIGH level clock period
4.0
−µs
tSU;STA
set-up time for START condition
repeated start
4.7
−µs
tHD;DAT
data hold time
for bus compatible masters
5
−µs
for bus devices
[1]
0
ns
tSU;DAT
data set-up time
250
ns
tr
SDA and SCL rise time
1
µs
tf
SDA and SCL fall time
300
ns
tSU;STO
set-up time for STOP condition
4.0
−µs


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