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PCF8574TS Datasheet(PDF) 7 Page - NXP Semiconductors |
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PCF8574TS Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 24 page  2002 Nov 22 7 Philips Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 6 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 6.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.5). 6.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Fig.6). 6.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.7). Fig.5 Bit transfer. handbook, full pagewidth MBC621 data line stable; data valid change of data allowed SDA SCL Fig.6 Definition of start and stop conditions. handbook, full pagewidth MBC622 SDA SCL P STOP condition SDA SCL S START condition Fig.7 System configuration. MBA605 MASTER TRANSMITTER / RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER / RECEIVER SDA SCL |
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