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ACS8510 Datasheet(PDF) 16 Page - Semtech Corporation |
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ACS8510 Datasheet(HTML) 16 Page - Semtech Corporation |
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16 / 69 page  Revision 2.07/Jan 2001 ã2001 Semtech Corp www.semtech.com 16 ACS8510 SETS ADVANCED COMMUNCIATIONS FINAL Figure 3: Wander and Jitter Transfer Characteristsics 3HDNWRSHDN MLWWHU DQG ZDQGHUDPSOLWXGH ORJ VFDOH -LWWHU DQG ZDQGHUIUHTXHQF\ ORJ VFDOH G% 8, # I G% -LWWHU FXWRII ORZ IUHTXHQF\ +] -LWWHU FXWRII KLJK IUHTXHQF\ +] store is required to prevent data loss. But, since any buffer store potentially increases latency, wander may often only need to be removed at specific points within a network where buffer stores are acceptable, such as at digital cross connects. Otherwise, wander is sometimes not required to be attenuated and can be passed through transparently. The ACS8510 has programmable wander transfer characteristics in a range from 0.1 Hz to 20 Hz. The wander and jitter transfer characteristic is shown in Figure 3. Wander on the local oscillator clock will not have significant effect on the output clock whilst in Locked mode, so long as the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In Free-Running or Holdover mode wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section Local Oscillator Clock. Phase Variation There will be a phase shift across the ACS8510 between the selected input reference source and the output clock. This phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterised using two parameters, MTIE (Maximum Time Interval Error), and TDEV (Time Deviation), which, although being specified in all relevent specifications, differ in acceptable limits in each one. Typical measurements for the ACS8510 are shown in Figures 4 and 5, for Locked mode operation. Figure 6 shows a typical measurement of Phase Error accumulation in Holdover mode operation. The required performance for phase variation during Holdover is specified in several ways depending upon the particular circumstances |
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