Applications Information

FPGAs or ASICs integrate the designed DSSHA1. Using

several modules, an achievable authentication method

makes a design secure. In Figure 5, the design module

with a microprocessor can offload the SHA-1 computa-

tion to the DSSHA1. In Figure 5, the designer first crafts

a randomly generated challenge and compares the

result from DSSHA1 to the response received from the

DS28E01. If the result and response match, then the

design has been authenticated and can enable the

product’s functionality. It is often desirable to make vari-

ations in the authentication process in software and

hardware. This makes successful attacks less likely.

Refer to Application Note 1098:

White Paper 3: Why are

1-Wire SHA-1 Devices Secure? for more information.

Memory-Mapped SHA-1 Coprocessor

_______________________________________________________________________________________

7

CLK

ADDR[4:0]

CSZ

WRZ

DATAO[31:0]

VALID DATA

VALID ADDRESS

DATAI[31:0]

Figure 4. Read Cycle

RESPONSE

CHALLENGE

DESIGN

MODULE

MICROPROCESSOR

TOP-LEVEL DESIGN MODULE

R

3.3V

MODULE

DSSHA1

MODULE

DS1WM

DS28E01-100

Figure 5. Typical FPGA or ASIC Application