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71M6515H Datasheet(PDF) 20 Page - Teridian Semiconductor Corporation |
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71M6515H Datasheet(HTML) 20 Page - Teridian Semiconductor Corporation |
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20 / 60 page  71M6515H Energy Meter IC DATA SHEET JULY 2011 Page: 20 of 60 © 2005 −2011 Teridian Semiconductor Corporation 1.6 A Maxim Integrated Products Brand Internal Resources Oscillator The oscillator drives a standard 32.768kHz watch crystal. Crystals of this type are accurate and do not require a high current oscillator circuit. The 71M6515H oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. Using PLL techniques, all internal clocks, such as the 4.915MHz clock for the ADC and the post-processor, are derived from the watch crystal frequency. Real-Time Clock (RTC) The RTC is driven directly by the crystal oscillator. In the absence of V3P3, it is powered by the battery-backed up supply. The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year. The nominal quadratic temperature coefficient of the crystal is automatically compensated in the RTC. The RTC is capable of processing leap years. I/O Peripherals The 71M6515H includes several I/O peripheral functions that improve the functionality of the device and reduce the component count for most meter applications. The I/O peripherals include a UART and digital I/O. Digital I/O The device includes eight pins of general purpose digital I/O (D0…D7). Each pin can be configured independently as an input or output with the D_DIR bits. Inputs are standard CMOS with no pull-ups or pull-downs. Outputs are standard CMOS. The DIO pins are controlled by the D_CONFIG register. Immediately after reset or power-up, D0 through D7 are in tri-state mode. 140 ms after reset, D0 through D7 are con- figured as outputs and driven low. UART Host Interface The UART is a dedicated 2-wire serial interface, which can communicate with the host processor. The operation of each pin is as follows: RX: Is the pin accepting the serial input data. It inputs data to internal registers. The bytes are input LSB first. The voltage applied to this pin must be restricted to 0 to 3.6V. TX: Is the pin used for serial output data. It outputs the contents of a block of internal registers. The bytes are output LSB first. BAUD_RATE: The baud rate can be selected with the BAUD_RATE pin (38.4bps when high, 19.2bps when low). UARTCSZ: This pin enables the UART when low. The UART can be reset by taking UARTCSZ briefly to the high state and then low again. The 71M6515H has several on-chip registers, which can be read and written. All transfers start with a stream of 8-bit bytes (LSB first) from the host on the RX input, followed by a (possibly null) stream of 8-bit bytes (LSB first) to the host on the TX output (see Figure 9 and Figure 10). The UART is configured as 8N1 (8 bits, no parity, 1 stop bit). If the READY bit in STMASK is enabled, the IRQZ pin can be used to signal data availability to the host. If data read cycles exceeding 1 second are used, care should be taken to prevent data overflow. UART Write Register Operation The registers are written by sending a byte, consisting of a starting register address in the seven MSBs and ‘0’ in the LSB indicating this is a write operation. It is followed by a one byte length of bytes to write. If more bytes arrive than fit in the addressed register, subsequent registers will be written. The bytes are processed in “big-endian” order (i.e. most significant byte first). See Figure 9 (read bits and bytes from left to right). |
Similar Part No. - 71M6515H_11 |
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Similar Description - 71M6515H_11 |
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