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PIC24F16KA102 Datasheet(PDF) 10 Page - Microchip Technology

Part # PIC24F16KA102
Description  Flash Programming Specifications
Download  48 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC24F16KA102 Datasheet(HTML) 10 Page - Microchip Technology

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PIC24FXXKAXXX
DS39919A-page 10
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© 2008 Microchip Technology Inc.
TABLE 3-4:
SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE
3.6
Writing Code Memory
The procedure for writing code memory is the same as
writing the Configuration registers. The difference is
that the 32 instruction words are programmed one at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed. Figure 3-8 illustrates the code
memory writing flow.
Table 3-5 provides the ICSP programming details,
including the serial pattern with the ICSP command
code, which must be transmitted LSB first, using the
PGCx and PGDx pins (see Figure 3-2).
In Step 1 of Table 3-5, the Reset vector is exited; in
Step 2,
the
NVMCON
register
is
initialized
for
programming a full row of code memory, and in Step 3,
the 24-bit starting destination address for programming
is loaded into the TBLPAG register and W7 register.
The upper byte of the starting destination address is
stored in TBLPAG and the lower 16 bits of the
destination address are stored in W7.
To
minimize
the
programming
time,
a
packed
instruction format is used (see Figure 3-7).
In Step 4 of Table 3-5, four packed instruction words
are stored in working registers, W0:W5, using the MOV
instruction; the Read Pointer, W6, is initialized.
Figure 3-7 illustrates the contents of W0:W5 holding
the packed instruction word data. In Step 5, eight
TBLWT
instructions are used to copy the data from
W0:W5 to the write latches of the code memory. Since
code memory is programmed 32 instruction words at a
time, Steps 3 to 5 are repeated eight times to load all
the write latches (see Step 6).
After the write latches are loaded, initiate programming
by writing to the NVMCON register in Steps 7 and 8. In
Step 9, the internal PC is reset to 200h. This is a
precautionary measure to prevent the PC from
incrementing to unimplemented memory when large
devices are being programmed. Finally, in Step 10,
repeat Steps 3 through 9 until all of the code memory is
programmed.
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
0x200
NOP
Step 2: Set the NVMCON to erase the entire program memory.
0000
0000
24064A
883B0A
MOV
#0x4064, W10
MOV
W10, NVMCON
Step 3: Set the TBLPAG and perform dummy table write to select the erased memory.
0000
0000
0000
0000
0000
0000
200000
880190
200000
BB0800
000000
000000
MOV
#<PAGEVAL>, W0
MOV
W0, TBLPAG
MOV
#0x0000, W0
TBLWTL W0, [W0]
NOP
NOP
Step 4: Initiate the erase cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NVMCON, #WR
NOP
NOP
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
0000
0001
0000
000000
040200
000000
803B02
883C22
000000
<VISI>
000000
NOP
GOTO
0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out the contents of the VISI register.
NOP


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