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PIC24F08KA102 Datasheet(PDF) 6 Page - Microchip Technology |
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PIC24F08KA102 Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 48 page  PIC24FXXKAXXX DS39919A-page 6 Advance Information © 2008 Microchip Technology Inc. 3.2.1 SIX SERIAL INSTRUCTION EXECUTION The SIX control code allows execution of PIC24FXXKAXXX family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGC clock cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-2). Coming out of Reset, the first 4-bit control code is always forced to SIX, and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up; thereby resulting in a 9-bit SIX command, instead of the normal 4-bit SIX command. After the forced SIX is clocked in, the ICSP operation resumes to normal. That is, the next 24 clock cycles load the first instruction word to the CPU. 3.2.1.1 Differences Between SIX Instruction Execution and Normal Instruction Execution There are some differences between executing instructions using the SIX ICSP command and normal device instruction execution. As a result, the code examples in this specification might not match those required to perform the same operations during normal device operation. The differences are: • Two-word instructions require 2 SIX operations to clock in all the necessary data. Examples of two-word instructions are GOTO and CALL . • Two-cycle instructions require 2 SIX operations to complete. The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation, which should shift in a NOP to avoid losing data, allows the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are table read and table write instructions. • The CPU does not automatically stall to account for pipeline changes. A CPU stall occurs when an instruction modifies a register, which is used by the instruction immediately following the CPU stall for Indirect Addressing. During normal operation, the CPU forces a NOP while the new data is read. To account for this, while using ICSP, any indirect references to a recently modified register should be proceeded with a NOP. For example, MOV #0x0,W0 followed by MOV [W0] ,W1 must have a NOP inserted in between. If a two-cycle instruction modifies a register, which is used indirectly, it requires two following NOPs; one to execute the second half of the instruction and the other to stall the CPU to correct the pipeline. For example, TBLWTL [W0++],[W1] should be followed by 2 NOPs. • The device Program Counter (PC) continues to automatically increment during the ICSP instruction execution, even though the Flash memory is not being used. As a result, it is possible for the PC to be incremented so that it points to invalid memory locations. Examples of invalid memory spaces are unimplemented Flash addresses or the vector space (location 0x0 to 0x1FF). If the PC ever points to these locations, it causes the device to reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method of achieving this is to perform a “GOTO 0x200”. 3.2.2 REGOUT SERIAL INSTRUCTION EXECUTION The REGOUT control code allows for the data to be extracted from the device in the ICSP mode. It is used to clock the contents of the VISI register out of the device over the PGDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles. After this, an additional 16 cycles are required to clock the data out (see Figure 3-3). The REGOUT code is unique as the PGDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGDx pin becomes an output as the VISI register is shifted out. Note: To account for this forced NOP, all example codes in this specification begin with a NOP to ensure that no data is lost. Note 1: After the contents of VISI are shifted out, the PIC24FXXKAXXX devices maintain PGDx as an output until the first rising edge of the next clock is received. 2: Data changes on the falling edge and latches on the rising edge of PGCx. For all data transmissions, the Least Significant bit (LSb) is transmitted first. |
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