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5V19EE604NDGI8 Datasheet(PDF) 11 Page - Integrated Device Technology |
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5V19EE604NDGI8 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 29 page IDT5V19EE604 EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR CLOCK SYNTHESIZER IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR 11 IDT5V19EE604 REV F 022310 PLL Loop Bandwidth: Charge pump gain (K φ⎞) = Ip / 2π VCO gain (KVCO) = 900 MHz/V * 2 π M = Total multiplier value (See the Reference Divider, Feedback Divider and Output Divider section for more detail) ωc = (Rz * Kφ * KVCO * Cz)/(M * (Cz + Cp)) Fc = ωc / 2π Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce the phase margin thus compromising loop stability. To determine if the loop is stable, the phase margin ( φm) needs to be calculated as follows. Phase Margin: ωz = 1 / (Rz * Cz) ωp = (Cz + Cp)/(Rz * Cz * Cp) φm = (360 / 2π) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)] To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability. |
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