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CYP15G0101DXB Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CYP15G0101DXB Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 44 page CYP15G0101DXB CYV15G0101DXB Document Number: 38-02031 Rev. *M Page 9 of 44 RXMODE 3-level select[7] static control input Receive operating mode. This input selects one of two RXST channel status reporting modes and is only interpreted when the decoder is enabled (DECMODE ≠ LOW). See Table 19 for details. FRAMCHAR 3-level select[7] static control input Framing character select. Used to select the character or portion of a character used for character framing of the received data streams. When MID, the framer looks for both positive and negative disparity versions of the eight-bit comma character. When HIGH, the framer looks for both positive and negative disparity versions of the K28.5 character. Configuring FRAMCHAR = LOW is reserved for component test. RFMODE 3-level select static control input[7] Reframe mode select. Used to select the type of character framing used to adjust the character boundaries (based on detection of one or more framing characters in the data stream. This signal operates in conjunction with the type of framing character selected. When LOW, the low-latency framer is selected. This will frame on each occurrence of the selected framing character(s) in the received data stream. This mode of framing stretches the recovered character-rate clock for one or multiple cycles to align that clock with the recovered data. When MID, the Cypress-mode multi-byte parallel framer is selected. This requires a pair of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits (five characters), before the character boundaries are adjusted. The recovered character clock remains in the same phase regardless of character offset. When HIGH, the alternate-mode multi-byte parallel framer is selected. This requires detection of the selected framing character(s) in the received data stream, on identical 10-bit boundaries, on four directly adjacent characters. The recovered character clock remains in the same phase regardless of character offset. PARCTL 3-level select static control input[7] Parity check/Generate control. Used to control the parity check and generate functions. When LOW, parity checking is disabled, and the RXOP output is disabled (high Z). When MID, and the 8B/10B encoder and decoder are enabled (TXMODE[1] ≠ LOW, DECMODE ≠ LOW), TXD[7:0] inputs are checked (along with TXOP) for valid ODD parity, and ODD parity is generated for the RXD[7:0] outputs and presented on RXOP. When the 8B/10B encoder and decoder are disabled (TXMODE[1] = LOW, DECMODE = LOW), the TXD[7:0] and TXCT[1:0] inputs are checked (along with TXOP) for valid ODD parity, and ODD parity is generated for the RXD[7:0] and RXST[1:0] outputs and presented on RXOP. When HIGH, parity generation and checking are enabled. The TXD[7:0] and TXCT[1:0] inputs are checked (along with TXOP) for valid ODD parity, and ODD parity is generated for the RXD[7:0] and RXST[2:0] outputs and presented on RXOP. See Table 2 and Table 15 for details. DECMODE 3-level select static control input[7] Decoder mode select. When LOW, the decoder is bypassed and raw 10-bit characters are passed to the output register. When the decoder is bypassed, RXCKSEL must be MID. When MID, the Cypress Decoder table for special code characters is used. When HIGH, the alternate Decoder table for special code characters is used. See Table 21 for a list of the special codes supported in both encoded modes. RXCKSEL 3-level select[7] static control input Receive clock mode. Selects the receive clock source used to transfer data to the output registers and configures the elasticity buffer in the receive path. When LOW, the output register is clocked by REFCLK. RXCLK ± and RXCLKC+ present buffered and delayed forms of REFCLK. When MID, the RXCLK ± output follows the recovered clock as selected by RXRATE and the elasticity buffer is bypassed. When the 10B/8B decoder and elasticity buffer are bypassed (DECMODE=LOW), RXCKSEL must be MID. Configuring RXCKSEL = HIGH is an invalid mode of operation. Note 7. 3-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH. The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). When not connected or allowed to float, a 3-level select input will self-bias to the MID level. Pin Descriptions CYP(V)15G0101DXB single-channel HOTLink II (continued) Pin Name I/O Characteristics Signal Description [+] Feedback |
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