CYDMX256A16, CYDMX256B16

CYDMX128A16, CYDMX128B16

CYDMX064A16, CYDMX064B16

Asynchronous Dual-Port Static RAM

Cypress Semiconductor Corporation

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198 Champion Court

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San Jose

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408-943-2600

Document #: 001-08090 Rev. *G

Revised May 2, 2011

16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM

Features

independent access

(ADM) interface

address and data interface

Notes

1. A13-A0 for CYDMX256A16 and CYDMX256B16; A12-A0 for CYDMX128A16 and CYDMX128B16; and A11-A0 for CYDMX064A16 and CYDMX064B16.

2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16.

Block Diagram

Mux'ed

Address /

Data

I/O Control

Address

Decode

Mux'ed

Address/

Data

I/O Control

I/OL15-I/OL8

I/OL7-I/OL0

Address

Decode

I/OR15-I/OR8

A13-A0 [note 1]

Control Logic

CS#L

OE#L

WE#L

BUSY#L

INT#L

BUSY#R

INT#R

CS#R

OE#R

WE#R

Dual Ported

Memory Array

16k/8k/4k x 16

ADV#L

UB#L

LB#L

DataL<15..0>

DataR<15..0>

AddrL<13..0>

AddrR<13..0>

ADV#R

UB#R

LB#R

MSEL

I/OR7-I/OR0

IRR/ODR

SFEN#

IRR1-IRR0 [note 2]

ODR4-ODR0

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