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CYDMX128A16 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CYDMX128A16 Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 25 page CYDMX256A16, CYDMX256B16 CYDMX128A16, CYDMX128B16 CYDMX064A16, CYDMX064B16 16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-08090 Rev. *G Revised May 2, 2011 16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM Features ■ True dual-ported memory block that allow simultaneous independent access ❐ One port with dedicated time multiplexed address and data (ADM) interface ❐ One port configurable to standard SRAM or time multiplexed address and data interface ■ 16 K/8 K/4 K × 16 memory configuration ■ High speed access ❐ 65 ns or 90 ns ADM interface ❐ 40 ns or 60 ns standard SRAM interface ■ Fully asynchronous operation ■ Port independent 1.8 V, 2.5 V, and 3.0 V IOs ■ Ultra low operating power ❐ Active: ICC = 15 mA (typical) at 90 ns ❐ Active: ICC = 25 mA (typical) at 65 ns ❐ Standby: ISB3 = 2 A (typical) ■ Port independent power down ■ On-chip arbitration logic ■ Mailbox interrupt for port to port communication ■ Input Read and Output Drive registers ■ Upper byte and lower byte control ■ Small package: 6 × 6 mm, 100-ball Pb-free BGA ■ Industrial temperature range Notes 1. A13-A0 for CYDMX256A16 and CYDMX256B16; A12-A0 for CYDMX128A16 and CYDMX128B16; and A11-A0 for CYDMX064A16 and CYDMX064B16. 2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16. Block Diagram Mux'ed Address / Data I/O Control Address Decode Mux'ed Address/ Data I/O Control I/OL15-I/OL8 I/OL7-I/OL0 Address Decode I/OR15-I/OR8 A13-A0 [note 1] Control Logic CS#L OE#L WE#L BUSY#L INT#L BUSY#R INT#R CS#R OE#R WE#R Dual Ported Memory Array 16k/8k/4k x 16 ADV#L UB#L LB#L DataL<15..0> DataR<15..0> AddrL<13..0> AddrR<13..0> ADV#R UB#R LB#R MSEL I/OR7-I/OR0 IRR/ODR SFEN# IRR1-IRR0 [note 2] ODR4-ODR0 [+] Feedback |
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Similar Description - CYDMX128A16 |
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