CYD04S72V

CYD09S72V

CYD18S72V

Document Number : 38-06069 Rev. *L

Page 6 of 30

Port IO power supply.

REV[18,19]L

REV[18,19]R

Reserved pins for future features.

MRST

Master reset input. MRST is an asynchronous input signal and affects both ports. A

master reset operation is required at power-up.

TRST[18,20]

JTAG reset input.

TMS

JTAG test mode select input. It controls the advance of JTAG TAP state machine.

State machine transitions occur on the rising edge of TCK.

TDI

JTAG test data input. Data on the TDI input will be shifted serially into selected

registers.

TCK

JTAG test clock input.

TDO

JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is

normally three-stated except when captured data is shifted out of the JTAG TAP.

Ground inputs.

Core power supply.

LVTTL power supply.

Notes

18. This ball will represent a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.

19. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales

20. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.

V. Please contact local Cypress FAE for more information

Left Port

Right Port

Description

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