CY62157EV30LL-55ZXE datasheet(10/21 Pages) CYPRESS

Part #	CY62157EV30LL-55ZXE

Description	8-Mbit (512 K x 16) Static RAM Automatic power down when deselected

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 21 page

CY62157EV30 MoBL®

Document #: 38-05445 Rev. *I

Page 10 of 21

Write Cycle No. 2 (CE1 or CE2 Controlled) [29, 30, 31]

Switching Waveforms (continued)

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 32

CE1

ADDRESS

CE2

WE

DATA I/O

OE

BHE/BLE

Notes

29. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate

a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that

terminates the write.

30. Data I/O is high impedance if OE = VIH.

31. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

32. During this period, the I/Os are in output state. Do not apply input signals.

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