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CY62157EV30LL-55ZSXE Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY62157EV30LL-55ZSXE
Description  8-Mbit (512 K x 16) Static RAM Automatic power down when deselected
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62157EV30LL-55ZSXE Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *I
Page 4 of 21
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................. –65 °C to + 150 °C
Ambient Temperature with
Power Applied ........................................ –55 °C to + 125 °C
Supply Voltage to Ground
Potential .............................–0.3 V to 3.9 V (VCCmax + 0.3 V)
DC Voltage Applied to Outputs
in High Z State [5, 6] ............–0.3 V to 3.9 V (VCCmax + 0.3 V)
DC Input Voltage [5, 6]........ –0.3 V to 3.9 V (VCC max + 0.3 V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ........................................> 2001 V
(MIL-STD-883, Method 3015)
Latch Up Current ...................................................> 200 mA
Operating Range
Device
Range
Ambient
Temperature
VCC [7]
CY62157EV30LL Industrial/
Auto-A
–40 °C to +85 °C 2.2 V to 3.6 V
Auto-E –40 °C to +125 °C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
45 ns (Industrial/
Auto-A)
55 ns (Auto-E)
Unit
Min Typ [8]
Max
Min Typ [8]
Max
VOH
Output HIGH voltage
IOH = –0.1 mA
2.0
2.0
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
2.4
V
VOL
Output LOW voltage
IOL = 0.1 mA
0.4
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
0.4
0.4
V
VIH
Input HIGH voltage
VCC = 2.2 V to 2.7 V
1.8
VCC + 0.3
1.8
VCC + 0.3
V
VCC = 2.7 V to 3.6 V
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VIL
Input LOW voltage
VCC = 2.2 V to 2.7 V
–0.3
0.6
–0.3
0.6
V
VCC = 2.7 V to 3.6 V
–0.3
0.8
–0.3
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
+1
–4
+4
A
IOZ
Output leakage current GND < VO < VCC, Output Disabled
–1
+1
–4
+4
A
ICC
VCC operating supply
current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
18
25
18
35
mA
f = 1 MHz
1.8
3
1.8
4
ISB1 [9]
Automatic CE power
down current — CMOS
inputs
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60 V
28–
2
30
A
ISB2 [9]
Automatic CE power
down current — CMOS
inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
28–
2
30
A
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100
s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other
inputs can be left floating.
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