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CY62177EV30 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY62177EV30
Description  32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62177EV30 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *H
Page 6 of 15
Switching Characteristics
Over the Operating Range
Parameter[17]
Description
55 ns
Unit
Min
Max
Read Cycle
tRC
Read cycle time
55
ns
tAA
Address to data valid
55
ns
tOHA
Data hold from address change
6
ns
tACE
CE1 LOW and CE2 HIGH to data valid
55
ns
tDOE
OE LOW to data valid
25
ns
tLZOE
OE LOW to LOW Z[18]
5–
ns
tHZOE
OE HIGH to High Z[18, 19]
–18
ns
tLZCE
CE1 LOW and CE2 HIGH to Low Z
[18]
10
ns
tHZCE
CE1 HIGH and CE2 LOW to High Z
[18, 19]
–18
ns
tPU
CE1 LOW and CE2 HIGH to power up
0
ns
tPD
CE1 HIGH and CE2 LOW to power down
55
ns
tDBE
BLE/BHE LOW to data valid
55
ns
tLZBE
BLE/BHE LOW to Low Z [18]
10
ns
tHZBE
BLE/BHE HIGH to HIGH Z [18, 19]
–18
ns
Write Cycle[20]
tWC
Write cycle time
55
ns
tSCE
CE1 LOW and CE2 HIGH to write end
40
ns
tAW
Address setup to write end
40
ns
tHA
Address hold from write end
0
ns
tSA
Address setup to write start
0
ns
tPWE
WE pulse width
40
ns
tBW
BLE/BHE LOW to write end
40
ns
tSD
Data setup to write end
25
ns
tHD
Data hold from Write End
0
ns
tHZWE
WE LOW to High Z[18, 19]
–20
ns
tLZWE
WE HIGH to Low Z[18]
10
ns
Notes
17. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to
VCC(typ), and output loading of the specified IOL/IOH as shown in Table 1 on page 5.
18. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
20. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.


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