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CY62138EV30 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY62138EV30
Description  2-Mbit (256 K x 8) MoBL Static RAM Automatic power down when deselected
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62138EV30 Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY62138EV30 MoBL®
2-Mbit (256 K × 8) MoBL® Static RAM
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-05577 Rev. *D
Revised June 16, 2011
2-Mbit (256 K × 8) MoBL® Static RAM
Features
Very high speed: 45 ns
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62138CV30
Ultra low standby power
Typical standby current: 1 A
Maximum standby current: 7 A
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Offered in Pb-free 36-ball ball grid array (BGA) package
Functional Description
The CY62138EV30 is a high performance CMOS static RAM
organized as 256K words by eight bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. The device can be put into standby mode reducing
power consumption when deselected (CE HIGH).
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
A1
COLUMN
DECODER
Data in Drivers
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
256K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
CE
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Logic Block Diagram
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