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CY62128EV30LL-45ZXI Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY62128EV30LL-45ZXI
Description  1-Mbit (128 K x 8) Static RAM Automatic power-down when deselected
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62128EV30LL-45ZXI Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY62128EV30 MoBL®
Document #: 38-05579 Rev. *J
Page 7 of 18
Switching Characteristics
Over the Operating Range
Parameter [14, 15]
Description
45 ns (Industrial)
Unit
Min
Max
Read Cycle
tRC
Read cycle time
45
ns
tAA
Address to data valid
45
ns
tOHA
Data hold from address change
10
ns
tACE
CE LOW to data valid
45
ns
tDOE
OE LOW to data valid
22
ns
tLZOE
OE LOW to low Z [16]
5–
ns
tHZOE
OE HIGH to high Z [16, 17]
–18
ns
tLZCE
CE LOW to low Z [16]
10
ns
tHZCE
CE HIGH to high Z [16, 17]
–18
ns
tPU
CE LOW to power-up
0
ns
tPD
CE HIGH to power-down
45
ns
Write Cycle [18]
tWC
Write cycle time
45
ns
tSCE
CE LOW to write end
35
ns
tAW
Address setup to write end
35
ns
tHA
Address hold from write end
0
ns
tSA
Address setup to write start
0
ns
tPWE
WE pulse width
35
ns
tSD
Data setup to write end
25
ns
tHD
Data hold from write end
0
ns
tHZWE
WE LOW to high Z [16, 17]
–18
ns
tLZWE
WE HIGH to low Z [16]
10
ns
Notes
14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5.
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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