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CY29946 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY29946 Datasheet(HTML) 1 Page - Cypress Semiconductor |
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CY29946 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-07286 Rev. *G Revised May 11, 2011 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer Features ■ 2.5 V or 3.3 V operation ■ 200-MHz clock support ■ Two LVCMOS-/LVTTL-compatible inputs ■ Ten clock outputs: drive up to 20 clock lines ■ 1× or 1/2× configurable outputs ■ Output three-state control ■ 250-ps max output-to-output skew ■ Pin-compatible with MPC946, MPC9446 ■ Available in commercial and industrial temperature range ■ 32-pin TQFP package Description The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are LVCMOS or LVTTL compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. The CY29946 is capable of generating 1× and 1/2× signals from a 1× source. These signals are generated and retimed internally to ensure minimal skew between the 1× and 1/2× signals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1× to1/2× outputs. The CY29946 outputs can also be three-stated via MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs. Block Diagram 0 1 /1 /2 R 0 1 /1 /2 R 0 1 /1 /2 R 3 3 4 QA0:2 QB0:2 QC0:3 DSELA DSELB DSELC MR/OE# TCLK1 TCLK0 TCLK_SEL [+] Feedback |
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