CY29350

2.5 V or 3.3 V, 200-MHz,

9-Output Clock Driver

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 38-07474 Rev. *C

Revised April 12, 2011

2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver

Features

Functional Description

The CY29350 is a low-voltage high-performance 200-MHz

PLL-based clock driver designed for high speed clock

distribution applications.

The CY29350 features Xtal and LVCMOS reference clock inputs

and provides nine outputs partitioned in four banks of 1, 1, 2, and

5 outputs. Bank A divides the VCO output by 2 or 4 while the

other banks divide by 4 or 8 per SEL(A:D) settings, see . These

dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1.

Each LVCMOS compatible output can drive 50

 series or

parallel terminated transmission lines. For series terminated

transmission lines, each output can drive one or two traces giving

the device an effective fanout of 1:18.

The PLL is ensured stable given that the VCO is configured to

run between 200 MHz to 500 MHz. This allows a wide range of

output frequencies from 25 MHz to 200 MHz. The internal VCO

is running at multiples of the input reference clock set by the

feedback divider, see Table 1.

When PLL_EN is LOW, PLL is bypassed and the reference clock

directly feeds the output dividers. This mode is fully static and the

minimum input clock frequency specification does not apply.

Block Diagram

OSC

Phase

Detector

VCO

200 -

500MHz

LPF











QA

QB

QC0

QC1

QD0

QD1

QD2

QD3

QD4

SELA

PLL_EN

TCLK

REF_SEL

XIN

XOUT

FB_SEL

SELB

SELC

OE#

SELD

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