CY22801KFXI datasheet(4/23 Pages) CYPRESS

Part #	CY22801KFXI

Description	Universal Programmable Clock Generator (UPCG) Integrated phase-locked loop (PLL)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY22801

Document #: 001-15571 Rev. *E

Page 4 of 23

External Reference Crystal/Clock Input

CY22801 can accept external reference clock input as well as

crystal input. External reference clock input frequency range is

from 1MHz to 133 MHz.

The input crystal oscillator of the CY22801 is an important

feature because of the flexibility it provides in selecting a crystal

as a reference clock source. The oscillator inverter has

programmable gain, enabling maximum compatibility with a

reference

crystal,

based

on

manufacturer,

process,

performance, and quality.

Input load capacitors are placed on the CY22801 die to reduce

external

component

cost.

These

capacitors

are

true

parallel-plate capacitors, designed to reduce the frequency shift

that occurs when non-linear load capacitance is affected by load,

bias, supply, and temperature changes.

The value of the input load capacitors is determined by eight bits

in a programmable register. Total load capacitance is determined

by the formula:

CapLoad = (CL – CBRD – CCHIP)/0.09375 pF

In CyClocksRT, enter the crystal capacitance (CL). The value of

CapLoad is determined automatically and programmed into the

CY22801.

Output Clock Frequencies

The CY22801 is a very flexible clock generator with up to three

individual outputs, generated from an integrated PLL.

See Figure 2 for details.

The output of the PLL runs at high frequency and is divided down

to generate the output clocks. Two programmable dividers are

available for this purpose. Therefore, although the output clocks

may have different frequencies, they must be related, based on

the PLL frequency.

It is also possible to direct the reference clock input to any of the

outputs, thereby bypassing the PLL. Lastly, the reference clock

may be passed through either divider.

Figure 2. Basic PLL Block Diagram

VCXO

One of the key components of the CY22801 device is the VCXO.

The VCXO is used to ‘pull’ the reference crystal higher or lower

to lock the system frequency to an external source. This is ideal

for applications where the output frequency needs to track along

with an external reference frequency that is constantly shifting.

A special pullable crystal must be used to have adequate VCXO

pull range. Pullable crystal specifications are included in this

datasheet.

VCXO is not compatible with Spread spectrum and Serial

Interface.

VCXO Profile

Figure 3 shows an example of a VCXO profile. The analog

voltage input is on the X-axis and the PPM range is on the Y-axis.

An increase in the VCXO input voltage results in a corresponding

increase in the output frequency. This moves the PPM from a

negative to positive offset.

Figure 3. VCXO Profile

Spread Spectrum Clock Generation (SSCG)

Spread spectrum clock generation (SSCG) in CY22801 helps to

reduce EMI found in today’s high-speed digital electronic

systems.

The device uses the proprietary spread spectrum clock (SSC)

technology to synthesize and modulate the frequency of the

input clock. By modulating the frequency of the clock, the

measured EMI at the fundamental and harmonic frequencies is

greatly reduced. This reduction in radiated energy can

significantly reduce the cost of complying with the regulatory

agency electromagnetic compatibility (EMC) requirements and

improve time to market without degrading system performance.

Programmed spread spectrum modulation will appear same on

all three clock outputs as they come from same PLL even if

operating at different frequencies. Spread spectrum is not

compatible with VCXO feature.

CLKC

Crosspoint

Switch

Matrix

REF

(XIN/CLKIN)

/P

PFD

VCO

/Q

CLKB

CLKA

Post

Divider

1N

Post

Divider

2N

-200

-150

-100

-50

0

50

100

150

200

00.5

11.5

22.5

33.5

VCXO input [V]

[+] Feedback

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