CY23EP05SXC-1HT datasheet(5/15 Pages) CYPRESS

Part #	CY23EP05SXC-1HT

Description	2.5 V or 3.3 V,10-220-MHz, Low Jitter, 5 Output Zero Delay Buffer

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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5 / 15 page

CY23EP05

Document #: 38-07759 Rev. *C

Page 5 of 15

Notes

7. For the given maximum loading conditions. See CL in Operating Conditions Table.

8. Parameter is guaranteed by design and characterization. Not 100% tested in production.

2.5-V DC Electrical Specifications

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VDD

Supply voltage

2.3

2.5

2.7

V

VIL

Input LOW voltage

–

0.7

V

VIH

Input HIGH voltage

1.7

–

VDD + 0.3

V

IIL

Input leakage current

0 < VIN < VDD

–10

–

10

μA

IIH

Input HIGH current

VIN = VDD

–

100

μA

VOL

Output LOW voltage

IOL = 8 mA (standard drive)

IOL = 12 mA (high drive)

–

–0.5

0.5

V

VOH

Output HIGH voltage

IOH = –8 mA (standard drive)

IOH = –12 mA (high drive)

VDD – 0.6

––

–

V

IDD (PD mode)

Power Down supply current

REF = 0 MHz (commercial)

–

12

μA

REF = 0 MHz (industrial)

–

25

μA

IDD

Supply current

Unloaded outputs, 66-MHz REF

–

45

mA

3.3-V and 2.5-V AC Electrical Specifications

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

1/t1

Maximum frequency[7]

(input/output)

3.3 V high drive

10

–

220

MHz

3.3 V standard drive

10

–

167

MHz

2.5 V high drive

10

–

200

MHz

2.5 V standard drive

10

–

133

MHz

TIDC

Input duty cycle

< 133.3 MHz

25

–

75

%

> 133.3 MHz

40

–

60

%

t2 ÷ t1

Output duty cycle[8]

< 133.3 MHz

47

–

53

%

> 133.3 MHz

45

–

55

%

t3,t4

Rise, fall time (3.3 V)[8]

Std drive, CL = 30 pF, < 100 MHz

–

1.6

ns

Std drive, CL = 22 pF, < 133.3 MHz

–

1.6

ns

Std drive, CL = 15 pF, < 167 MHz

–

0.6

ns

High drive, CL = 30 pF, < 100 MHz

–

1.2

ns

High drive, CL = 22 pF, < 133.3 MHz

–

1.2

ns

High drive, CL = 15 pF, > 133.3 MHz

–

0.5

ns

t3, t4

Rise, fall time (2.5 V)[8]

Std drive, CL = 15 pF, < 133.33 MHz

–

1.5

ns

High drive, CL = 30 pF, < 100 MHz

–

2.1

ns

High drive, CL = 22 pF, < 133.3 MHz

–

1.3

ns

High drive, CL = 15 pF, > 133.3 MHz

–

1.2

ns

t5

Output to output skew [8]

All outputs equally loaded

–

30

100

ps

t6

Delay, REF rising edge to

CLKOUT rising edge[8]

PLL enabled at 3.3 V

–100

–

100

ps

PLL enabled at 2.5 V

–200

–

200

ps

t7

Part to part skew[8]

Measured at VDD/2.

Any output to any output, 3.3 V supply

–150

–

150

ps

Measured at VDD/2.

Any output to any output, 2.5 V supply

–300

–

300

ps

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