CY14V104LA-BA45XIT datasheet(4/22 Pages) CYPRESS

Part #	CY14V104LA-BA45XIT

Description	4-Mbit (512 K x 8 / 256 K x 16) nvSRAM 25 ns and 45 ns access times

Download	22 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

Logo

4 / 22 page

CY14V104LA

CY14V104NA

Document #: 001-53954 Rev. *F

Page 4 of 22

Device Operation

The CY14V104LA/CY14V104NA nvSRAM is made up of two

functional components paired in the same physical cell. They are

a SRAM memory cell and a non-volatile QuantumTrap cell. The

SRAM memory cell operates as a standard fast static RAM. Data

in the SRAM is transferred to the non-volatile cell (the STORE

operation), or from the non-volatile cell to the SRAM (the

RECALL operation). Using this unique architecture, all cells are

stored and recalled in parallel. During the STORE and RECALL

operations, SRAM read and write operations are inhibited. The

CY14V104LA/CY14V104NA supports infinite reads and writes

similar to a typical SRAM. In addition, it provides infinite RECALL

operations from the non-volatile cells and up to 1 million STORE

operations. See Truth Table For SRAM Operations on page 17

for a complete description of read and write modes.

SRAM Read

The CY14V104LA/CY14V104NA performs a read cycle when

CE and OE are LOW and WE and HSB are HIGH. The address

specified on pins A0–18 or A0–17 determines which of the 524,288

data bytes or 262,144 words of 16 bits each are accessed. Byte

enables (BHE, BLE) determine which bytes are enabled to the

output, in the case of 16-bit words. When the read is initiated by

an address transition, the outputs are valid after a delay of tAA

(read cycle 1). If the read is initiated by CE or OE, the outputs

are valid at tACE or at tDOE, whichever is later (read cycle 2). The

data output repeatedly responds to address changes within the

tAA access time without the need for transitions on any control

input pins. This remains valid until another address change or

until CE or OE is brought HIGH, or WE or HSB is brought LOW.

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB

is HIGH. The address inputs must be stable before entering the

write cycle and must remain stable until CE or WE goes HIGH at

the end of the cycle. The data on the common I/O pins DQ0–15

are written into the memory if the data is valid tSD before the end

of a WE controlled write or before the end of an CE controlled

write. The Byte Enable inputs (BHE, BLE) determine which bytes

are written, in the case of 16-bit words. It is recommended that

OE be kept HIGH during the entire write cycle to avoid data bus

contention on common I/O lines. If OE is left LOW, internal

circuitry turns off the output buffers tHZWE after WE goes LOW.

AutoStore Operation

The CY14V104LA/CY14V104NA stores data to the nvSRAM

using one of the following three storage operations: Hardware

Store activated by HSB; Software Store activated by an address

sequence; AutoStore on device power-down. The AutoStore

operation is a unique feature of QuantumTrap technology and is

enabled by default on the CY14V104LA/CY14V104NA.

During a normal operation, the device draws current from VCC to

charge a capacitor connected to the VCAP pin. This stored

charge is used by the chip to perform a single STORE operation.

If the voltage on the VCC pin drops below VSWITCH, the part

automatically disconnects the VCAP pin from VCC. A STORE

operation is initiated with power provided by the VCAP capacitor.

Note If a capacitor is not connected to VCAP pin, AutoStore

must be disabled using the soft sequence specified in Preventing

AutoStore on page 6. If AutoStore is enabled without a capacitor

on VCAP pin, the device attempts an AutoStore operation without

sufficient charge to complete the Store. This may corrupt the data

stored in nvSRAM.

Figure 2 shows the proper connection of the storage capacitor

(VCAP) for automatic store operation. Refer to DC Electrical

Characteristics on page 8 for the size of VCAP. The voltage on

the VCAP pin is driven to VCC by a regulator on the chip. A pull-up

should be placed on WE to hold it inactive during power-up. This

pull-up is effective only if the WE signal is tristate during

power-up. Many MPUs tristate their controls on power-up. This

should be verified when using the pull-up. When the nvSRAM

comes out of power-on-recall, the MPU must be active or the WE

held inactive until the MPU comes out of reset.

To reduce unnecessary non-volatile stores, AutoStore and

hardware store operations are ignored unless at least one write

operation has taken place since the most recent STORE or

RECALL cycle. Software initiated STORE cycles are performed

regardless of whether a write operation has taken place. The

HSB signal is monitored by the system to detect if an AutoStore

cycle is in progress.

Figure 2. AutoStore Mode

Hardware STORE Operation

The CY14V104LA/CY14V104NA provides the HSB pin to control

and acknowledge the STORE operations. Use the HSB pin to

request a hardware STORE cycle. When the HSB pin is driven

LOW, the CY14V104LA/CY14V104NA conditionally initiates a

STORE operation after tDELAY. An actual STORE cycle only

begins if a write to the SRAM has taken place since the last

STORE or RECALL cycle. The HSB pin also acts as an open

drain driver (internal 100 k

 weak pull-up resistor) that is

internally driven LOW to indicate a busy condition when the

STORE (initiated by any means) is in progress.

Note After each Hardware and Software STORE operation

HSB is driven HIGH for a short time (tHHHD) with standard output

high current and then remains HIGH by internal 100 k

 pull-up

resistor.

SRAM write operations that are in progress when HSB is driven

LOW by any means are given time (tDELAY) to complete before

the STORE operation is initiated. However, any SRAM write

cycles requested after HSB goes LOW are inhibited until HSB

returns HIGH. In case the write latch is not set, HSB is not driven

LOW by the CY14V104LA/CY14V104NA. But any SRAM read

and write cycles are inhibited until HSB is returned HIGH by MPU

or other external source.

0.1 uF

VCC

VCAP

WE

VCAP

VSS

VCCQ

VCC

0.1 uF

[+] Feedback

Similar Part No. - CY14V104LA-BA45XIT

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY14V101LA	921Kb / 22P	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
	CY14V101LA-BA25XI	921Kb / 22P	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
	CY14V101LA-BA25XIT	921Kb / 22P	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
	CY14V101LA-BA45XI	921Kb / 22P	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles
	CY14V101LA-BA45XIT	921Kb / 22P	1-Mbit (128 K x 8/64 K x 16) nvSRAM Infinite read, write, and recall cycles

More results

Similar Description - CY14V104LA-BA45XIT

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY14B104LA_1106	961Kb / 25P	4-Mbit (512 K x 8/256 K x 16) nvSRAM 20 ns, 25 ns, and 45 ns access times
	CY14B104K_1106	1Mb / 35P	4-Mbit (512 K x 8/256 K x 16) nvSRAM with Real Time Clock 25 ns and 45 ns access times
	CY14B104NA-ZS25XI	988Kb / 26P	4-Mbit (512 K x 8/256 K x 16) nvSRAM
	STK12C68	1Mb / 24P	64 Kbit (8K x 8) AutoStore nvSRAM 25 ns, 35 ns, and 45 ns access times
	CY14B104LA	977Kb / 26P	4-Mbit (512 K 횞 8/256 K 횞 16) nvSRAM
	CY14B104LA	991Kb / 24P	4-Mbit (512 K 횞 8/256 K 횞 16) nvSRAM
	CY14B108K	1,014Kb / 31P	8 Mbit (1024 K x 8/512 K x 16) nvSRAM with Real Time Clock
	CY14B108K_1106	1Mb / 33P	8-Mbit (1024 K x 8/512 K x 16) nvSRAM with Real Time Clock
	CY14B108L_1106	952Kb / 25P	8-Mbit (1024 K x 8/512 K x 16) nvSRAM Infinite Read, Write, and RECALL cycles
	CG7501AA	498Kb / 20P	4-Mbit (512 K 횞 8) nvSRAM

More results

CY14V104LA-BA45XIT Datasheet(PDF) 4 Page - Cypress Semiconductor

CY14V104LA-BA45XIT Datasheet(HTML) 4 Page - Cypress Semiconductor

Similar Part No. - CY14V104LA-BA45XIT

Similar Description - CY14V104LA-BA45XIT

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL