CY14B108N-BA45XIT datasheet(6/25 Pages) CYPRESS

Part #	CY14B108N-BA45XIT

Description	8-Mbit (1024 K x 8/512 K x 16) nvSRAM Infinite Read, Write, and RECALL cycles

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Manufacturer	CYPRESS [Cypress Semiconductor]

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6 / 25 page

CY14B108L

CY14B108N

Document #: 001-45523 Rev. *J

Page 6 of 25

SRAM write operations that are in progress when HSB is driven

LOW by any means are given time (tDELAY) to complete before

the STORE operation is initiated. However, any SRAM write

cycles requested after HSB goes LOW are inhibited until HSB

returns HIGH. In case the write latch is not set, HSB is not driven

LOW by the CY14B108L/CY14B108N. But any SRAM read and

write cycles are inhibited until HSB is returned HIGH by MPU or

other external source.

During any STORE operation, regardless of how it is initiated,

the CY14B108L/CY14B108N continues to drive the HSB pin

LOW, releasing it only when the STORE is complete. Upon

completion of the STORE operation, the nvSRAM memory

access is inhibited for tLZHSB time after HSB pin returns HIGH.

Leave the HSB unconnected if it is not used.

Hardware RECALL (Power-Up)

During

power-up

or

after

any

low

power

condition

(VCC<VSWITCH), an internal RECALL request is latched. When

VCC again exceeds the VSWITCH on power-up, a RECALL cycle

is automatically initiated and takes tHRECALL to complete. During

this time, the HSB pin is driven LOW by the HSB driver and all

reads and writes to nvSRAM are inhibited.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by

a software address sequence. The CY14B108L/CY14B108N

Software STORE cycle is initiated by executing sequential CE or

OE controlled read cycles from six specific address locations in

exact order. During the STORE cycle an erase of the previous

nonvolatile data is first performed, followed by a program of the

nonvolatile elements. After a STORE cycle is initiated, further

input and output are disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used

for STORE initiation, it is important that no other read or write

accesses intervene in the sequence, or the sequence is aborted

and no STORE or RECALL takes place.

To initiate the Software STORE cycle, the following read

sequence must be performed.

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x8FC0 Initiate STORE cycle

The software sequence may be clocked with CE controlled reads

or OE controlled reads, with WE kept HIGH for all the six READ

sequences. After the sixth address in the sequence is entered,

the STORE cycle commences and the chip is disabled. HSB is

driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is

activated again for the read and write operation.

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by

a software address sequence. A software RECALL cycle is

initiated with a sequence of read operations in a manner similar

to the software STORE initiation. To initiate the RECALL cycle,

the following sequence of CE or OE controlled read operations

must be performed.

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x4C63 Initiate RECALL cycle

Internally, RECALL is a two-step procedure. First, the SRAM

data is cleared; then, the nonvolatile information is transferred

into the SRAM cells. After the tRECALL cycle time, the SRAM is

again ready for read and write operations. The RECALL

operation does not alter the data in the nonvolatile elements.

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CY14B108N-BA45XIT Datasheet(PDF) 6 Page - Cypress Semiconductor

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