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CY14B064I-SFXIT Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY14B064I-SFXIT Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 41 page PRELIMINARY CY14C064I CY14B064I, CY14E064I Document #: 001-68169 Rev. ** Page 6 of 41 High-Speed Mode (Hs-mode) In Hs-mode, nvSRAM can transfer data at bit rates of up to 3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place the device into high-speed mode. This enables master/slave communication for speed up to 3.4 MHz. A stop condition will exit Hs-mode. Serial Data Format in Hs-mode Serial data transfer format in Hs-mode meets the standard-mode I2C-bus specification. Hs-mode can only commence after the following conditions (all of which are in F/S-modes): 1. START condition (S) 2. 8-bit master code (0000 1XXXb) 3. No-acknowledge bit (A) Single and multiple-byte reads and writes are supported. After the device enters into Hs-mode, data transfer continues in Hs-mode until stop condition is sent by master device. The slave switches back to F/S-mode after a STOP condition (P). To continue data transfer in Hs-mode, the master sends Repeated START (Sr). See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode timings for read and write operation. Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth S START Condition 9 8 2 1 Clock pulse for acknowledgement Not acknowledge (A) Acknowledge (A) DATA OUTPUT BY MASTER DATA OUTPUT BY SLAVE SCL FROM MASTER Figure 6. Data Transfer Format in Hs-mode handbook, full pagewidth F/S-mode Hs-mode F/S-mode AA / A A DATA n (bytes +ack.) W / R S MASTER CODE Sr SLAVE ADD. Hs-mode continues Sr SLAVE ADD. P [+] Feedback |
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