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CY14B256P-SFXI Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY14B256P-SFXI Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 36 page  CY14B256P Document Number: 001-53881 Rev. *F Page 6 of 36 Serial Peripheral Interface SPI Overview The SPI is a four-pin interface with chip select (CS), serial input (SI), serial output (SO), and serial clock (SCK) pins. CY14B256P provides serial access to nvSRAM through SPI interface. The SPI bus on CY14B256P can run at speeds of up to 40 MHz for all instructions except RDRTC which runs at 25 MHz. The SPI is a synchronous serial interface which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on SPI bus is activated using the CS pin. The relationship between chip select, clock, and data is dictated by the SPI mode. CY14B256P supports SPI modes 0 and 3. In both these modes, data is clocked into the nvSRAM on the rising edge of SCK starting from the first rising edge after CS goes active. The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS is activated the first byte transferred from the bus master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued. The commonly used terms used in SPI protocol are as follows. SPI Master The SPI master device controls the operations on a SPI bus. A SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices using the CS pin. All the operations must be initiated by the master activating a slave device by pulling the CS pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are synchronized with this clock. SPI Slave The SPI slave device is activated by the master through the chip select line. A slave device gets the SCK as an input from the SPI master and all the communication is synchronized with this clock. SPI slave never initiates a communication on the SPI bus and acts on the instruction from the master. CY14B256P operates as a slave device and may share the SPI bus with multiple CY14B256P devices or other SPI devices. Chip Select (CS) For selecting any slave device, the master needs to pull-down the corresponding CS pin. Any instruction can be issued to a slave device only when the CS pin is LOW. The CY14B256P is selected when the CS pin is LOW. When the device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high-impedance state. Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each active chip select cycle. Serial Clock (SCK) Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW. CY14B256P allows SPI modes 0 and 3 for data communication. In both these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first bit (MSB) of SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK. Data Transmission SI and SO SPI data bus consists of two lines, SI and SO, for serial data communication. The SI is also referred to as Master Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier. CY14B256P has two separate pins for SI and SO which can be connected with the master as shown in Figure 3 on page 7. Most Significant Bit (MSB) The SPI protocol requires that the first bit to be transmitted is the most significant bit (MSB). This is valid for both address and data transmission. The 256-Kbit serial nvSRAM requires a 2-byte address for any read or write operation. However, because the address is only 15 bits, it implies that the first MSB which is fed in is ignored by the device. Although this bit is ‘don’t care’, Cypress recommends that this bit is treated as 0 to enable seamless transition to higher memory densities. Serial Opcode After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. CY14B256P uses the standard opcodes for memory accesses. In addition to the memory accesses, CY14B256P provides additional opcodes for the nvSRAM specific functions: STORE, RECALL, AutoStore Enable, and AutoStore Disable. Refer to Table 2 on page 8 for details on opcodes. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin till the next falling edge of CS and the SO pin remains tri-stated. Status Register CY14B256P has an 8-bit Status Register. The bits in the Status Register are used to configure the SPI bus. These bits are described in the Table 4 on page 9. |
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