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CY8CLED02 Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY8CLED02 Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 53 page CY8CLED16 Document Number: 001-13105 Rev. *H Page 9 of 53 Pin Information Pinouts The CY8CLED16 device is available in three packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, VDD, SMP, and XRES are not capable of Digital I/O. 28-Pin Part Pinout Table 2. 28-Pin Part Pinout (SSOP) Pin No. Type Pin Name Description Figure 3. 28-Pin Device Digital Analog 1 I/O I P0[7] Analog column mux input. 2 I/O I/O P0[5] Analog column mux input and column output. 3 I/O I/O P0[3] Analog column mux input and column output. 4 I/O I P0[1] Analog column mux input. 5 I/O P2[7] 6 I/O P2[5] 7 I/O I P2[3] Direct switched capacitor block input. 8 I/O I P2[1] Direct switched capacitor block input. 9 Power SMP Switch mode pump (SMP) connection to external components required. 10 I/O P1[7] I2C serial clock (SCL). 11 I/O P1[5] I2C serial data (SDA). 12 I/O P1[3] 13 I/O P1[1] Crystal (XTALin), I2C serial clock (SCL), ISSP-SCLK[1]. 14 Power Vss Ground connection. 15 I/O P1[0] Crystal (XTALout), I2C serial data (SDA), ISSP-SDATA[1]. 16 I/O P1[2] 17 I/O P1[4] optional external clock input (EXTCLK). 18 I/O P1[6] 19 Input XRES Active high external reset with internal pull- down. 20 I/O I P2[0] Direct switched capacitor block input. 21 I/O I P2[2] Direct switched capacitor block input. 22 I/O P2[4] External analog ground (AGND). 23 I/O P2[6] External voltage reference (VREF). 24 I/O I P0[0] Analog column mux input. 25 I/O I/O P0[2] Analog column mux input and column output. 26 I/O I/O P0[4] Analog column mux input and column output. 27 I/O I P0[6] Analog column mux input. 28 Power VDD Supply voltage. LEGEND: A = Analog, I = Input, and O = Output. A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Note 1. These are the ISSP pins, which are not High Z at POR. |
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Similar Description - CY8CLED02 |
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