CY8C20111, CY8C20121

Document Number: 001-53516 Rev. *G

Page 10 of 43

8.1 OUTPUT_STATUS

Output Status Register

OUTPUT_STATUS: 00h

The Output Status register represents the actual logical levels on the output pins.

8.2 OUTPUT_PORT

Output Port Register

OUTPUT_PORT: 04h

This register is used to write data to DIG output port. Pins defined as output of combinational logic (in OP_SEL_x register) cannot be

changed using this register.

8.3 CS_ENABLE

Select CapSense Input Register

CS_ENABLE: 07h

(

Writable only in Setup mode)

1 Button

7654321

0

Access: FD

R:01

Bit Name

STS[0]

2 Button

7654321

0

Access: FD

R:03

Bit Name

STS[1:0]

Bit

Name

Description

1:0

STS [1:0]

Used to represent the output status

0

Output low

1

Output high

1 Button

7654321

0

Access: FD

W:01

Bit Name

DIG[0]

2 Button

7654321

0

Access: FD

W:03

Bit Name

DIG[1:0]

Bit

Name

Description

1:0

DIG [1:0]

A bit set in this register sets the logic level of the output.

0

Logic ‘0’

1

Logic ‘1’

1 Button

7654321

0

Access: FD

RW:01

Bit Name

CS[0]

2 Button

7654321

0

Access: FD

RW:03

Bit Name

CS[1:0]

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