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CY8C20121 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY8C20121 Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 43 page  CY8C20111, CY8C20121 Document Number: 001-53516 Rev. *G Page 6 of 43 5.5 Circuit-5: Powering Down CapSense Express Device for Low Power Requirements For low power requirements, if VDD is to be turned off, the above concept can be used. The VDDs of CapSense Express, I 2C pull-ups, and LEDs must be from the same source. Turning off the VDD ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port pins can cater to the power supply requirement of the circuit, the LDO can be avoided. 6. Operating Modes 6.1 Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowl- edgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D are given only read access. Writing to these registers can be done only in setup mode. 6.2 Setup Mode All registers have read and write access (except those which are read only) in this mode. The acknowledgment times are longer compared to normal mode. When CapSense scanning is disabled (command code 0x0A in command register 0xA0), the acknowledgment times can be improved to values similar to the normal mode of operation. 7. I2C Interface The CapSense Express devices support the industry standard I2C protocol, which can be used to: ■ Configure the device ■ Read the status and data registers of the device ■ Control device operation ■ Execute commands The I2C address can be modified during configuration. 7.1 I2C Device Addressing The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending one byte address; first 7-bit contains address and LSb indicates the data transfer direction. Zero in the LSb indicates the write transaction form master and one indicates read transfer by the master. Table 3 shows example for different I2C addresses. Master Or Host LDO CapSense Express I2C Pull UPs LED I2C BUS SDA SCL VDD Output Output enable Table 3. I2C Addresses 7 Bit Slave Address (in Dec) D7 D6 D5 D4 D3 D2 D1 D0 8 Bit Slave Address (in Hex) 1 000 0 0 0 1 0(W) 02 1 0 0 0 0 0 0 1 1(R) 03 75 1 0 0 1 0 1 1 0(W) 96 75 1 0 0 1 0 1 1 1(W) 97 [+] Feedback |
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