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CY8C55_1106 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY8C55_1106 Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 114 page PRELIMINARY PSoC® 5: CY8C55 Family Datasheet Document Number: 001-66235 Rev. *A Page 6 of 114 Figure 2-1. 68-pin QFN Part Pinout[4] (GPIO) P2[6] (GPIO) P2[7] (SIO) P12[4] (SIO) P12[5] Vssb Ind Vboost Vbat Vssd XRES (SWDIO, GPIO) P1[0] (SWDCK, GPIO) P1[1] (GPIO) P1[2] (SWV, GPIO) P1[3] (GPIO) P1[4] (GPIO) P1[5] Vddio1 P0[3] (GPIO, OpAmp0-/Extref0) P0[2] (GPIO, OpAmp0+) P0[1] (GPIO, OpAmp0out) P0[0] (GPIO, OpAmp2out) P12[3] (SIO) P12[2] (SIO) Vssd Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO) P12[0] (SIO) P3[7] (GPIO, OpAmp3out) P3[6] (GPIO, OpAmp1out) Vddio3 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 QFN (Top View) Lines show Vddio to I/O supply association Notes 3. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. 4. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. [+] Feedback |
Similar Part No. - CY8C55_1106 |
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Similar Description - CY8C55_1106 |
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