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CY8C54_1106 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C54_1106 Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 105 page PRELIMINARY PSoC® 5: CY8C54 Family Datasheet Document Number: 001-66238 Rev. *A Page 3 of 105 1. Architectural Overview Introducing the CY8C54 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C54 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Digital Filter Block LCD Direct Drive CapSense Temperature Sensor 4 x Opamp + - ADCs 4 x DAC 4 x SC/CT Blocks ( TIA, PGA, Mixer etc) 4 x CMP + - System Wide Resources Program Debug Trace Program & Debug 8051or Cortex M3CPU Interrupt Controller PHUB DMA Cache Controller SRAM FLASH EEPROM Digital Interconnect Analog Interconnect 1.8 to 3.6 V ( Optional) 425 MHz (Optional) Xtal Osc 32.768 KHz ( Optional) RTC Timer IMO WDT and Wake ILO Clocking System 1.8V LDO SMP POR and LVD Sleep Power Power Management System USB PHY 3 per Opamp 2 x SAR ADC CAN 2.0 I2C Master/ Slave Universal Digital Block Array (24 x UDB) 4 x Timer Counter PWM FS USB 2.0 UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UART Logic 12- Bit PWM I2C Slave 8- Bit SPI 12- Bit SPI Logic 8- Bit Timer 16- Bit PRS UDB 8- Bit Timer Quadrature Decoder 16-Bit PWM UDB UDB UDB UDB UDB UDB UDB UDB 22 Ω Digital System Memory System System Bus CPU System Analog System to [+] Feedback |
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Similar Description - CY8C54_1106 |
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