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CY8C5368AXI-106 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY8C5368AXI-106 Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 106 page  PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-66237 Rev. *A Page 5 of 106 The CY8C53 family supports a wide supply operating range from 2.7 to 5.5 V. This allows operation from regulated supplies such as 3.3 V ± 10% or 5.0 V ± 10%, or directly from a wide range of battery types. It also provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 1.8 V. The designer can use the boost converter to generate other voltages required by the device, such as a 3.3 V supply for LCD glass drive. The boost’s output is available on the VBOOST pin, allowing other devices in the application to be powered from the PSoC. PSoC supports a wide range of low-power modes. These include a 1-µA hibernate mode with RAM retention and a 3-µA sleep mode with RTC. In the second mode the optional 32.768 KHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 2 mA when the CPU is running at 6 MHz. The details of the PSoC power modes are covered in the “Power System” section on page 22 of this data sheet. PSoC uses a SWD interface for programming, debug, and test. Using this standard interface enables the designer to debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. The Cortex-M3 debug and trace modules include FPB, DWT, and ITM. These modules have many features to help solve difficult debug and trace problems. Details of the programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page 54 of this data sheet. 2. Pinouts The VDDIO pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in Figure 2-1 and Figure 2-2. Using the VDDIO pins, a single PSoC can support multiple interface voltage levels, eliminating the need for off-chip level shifters. Each VDDIO may sink up to 100 mA total to its associated I/O pins and opamps. On the 68-pin and 100-pin devices each set of VDDIO associated pins may sink up to 100 mA. [+] Feedback |
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