CY8C20X36A/46A/66A/96A

Document Number: 001-54459 Rev. *E

Page 9 of 43

24-Pin QFN with USB

Pin No.

Type

Name

Description

Figure 4. CY8C20396A PSoC Device

Digital

Analog

1

I/O

I

P2[5]

2

I/O

I

P2[3]

3

I/O

I

P2[1]

4

IOHR

I

P1[7]

5

IOHR

I

P1[5]

6

IOHR

I

P1[3]

SPI CLK

7

IOHR

I

P1[1]

MOSI

8

Power

Ground

9

I/O

I

D+

USB D+

10

I/O

I

D-

USB D-

11

Power

Supply

12

IOHR

I

P1[0]

CLK[10]

13

IOHR

I

P1[2]

14

IOHR

I

P1[4]

Optional external clock input

(EXTCLK)

15

IOHR

I

P1[6]

16

RESET INPUT

XRES

Active high external reset with

internal pull-down

17

IOH

I

P0[0]

18

IOH

I

P0[2]

19

IOH

I

P0[4]

20

IOH

I

P0[6]

21

IOH

I

P0[7]

22

IOH

I

P0[5]

23

IOH

I

P0[3]

Integrating input

24

IOH

I

P0[1]

Integrating input

CP

Power

Thermal pad must be

connected to Ground

LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output

AI, I2C SDA , SPI MISO,P1[5]

QFN

(Top View)

AI, I 2 C SCL, SPI SS,P1[7]

AI, SPI CLK ,P1[3]

1

2

3

4

5

6

18

17

16

15

14

13

P0[0], AI

XRES

P0[2], AI

P2[1], AI

P1[2 ], AI

P1[4] , AI, EXTCLK

P1[6], AI

P2[5], AI

P2[3], AI

Notes

it must be electrically floated and not connected to any other signal.

9. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

10. Alternate SPI clock.

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