CY8C20236A-24LKXI datasheet(4/43 Pages) CYPRESS

Part #	CY8C20236A-24LKXI

Description	CapSense Applications Operating Range: 1.71 V to 5.5 V

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY8C20X36A/46A/66A/96A

Document Number: 001-54459 Rev. *E

Page 4 of 43

PSoC® Functional Overview

The PSoC family consists of on-chip controller devices, which

are designed to replace multiple traditional microcontroller unit

(MCU)-based components with one, low cost single-chip

programmable component. A PSoC device includes

configurable analog and digital blocks, and programmable

interconnect. This architecture allows the user to create

customized peripheral configurations, to match the requirements

of each individual application. Additionally, a fast CPU, Flash

program memory, SRAM data memory, and configurable I/O are

included in a range of convenient pinouts.

The architecture for this device family, as shown in the Logic

Block Diagram on page 2, consists of three main areas:

■ The Core

■ CapSense Analog System

■ System Resources (including a full-speed USB port).

A common, versatile bus allows connection between I/O and the

analog system.

Each CY8C20x36A/46A/66A/96A PSoC device includes a

dedicated CapSense block that provides sensing and scanning

control circuitry for capacitive sensing applications. Depending

on the PSoC package, up to 36 GPIO are also included. The

GPIO provides access to the MCU and analog mux.

PSoC Core

The PSoC Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO and

ILO. The CPU core, called the M8C, is a powerful processor with

speeds up to 24 MHz. The M8C is a 4-MIPS,

8-bit Harvard-architecture microprocessor.

CapSense System

The analog system contains the capacitive sensing hardware.

Several hardware algorithms are supported. This hardware

performs capacitive sensing and scanning without requiring

external components. The analog system is composed of the

CapSense PSoC block and an internal 1 V or 1.2 V analog

reference, which together support capacitive sensing of up to

33 inputs[2]. Capacitive sensing is configurable on each GPIO

pin. Scanning of enabled CapSense pins are completed quickly

and easily across multiple ports.

SmartSense™

SmartSense is an innovative solution from Cypress that removes

manual tuning of CapSense applications. This solution is easy to

use and provides a robust noise immunity. It is the only auto-

tuning solution that establishes, monitors, and maintains all

required tuning parameters. SmartSense allows engineers to go

from prototyping to mass production without re-tuning for

manufacturing variations in PCB and/or overlay material

properties.

Figure 1. CapSense System Block Diagram

Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin. Pins are

connected to the bus individually or in any combination. The bus

also connects to the analog system for analysis with the

CapSense block comparator.

Switch control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

■ Complex capacitive sensing interfaces, such as sliders and

touchpads.

■ Chip-wide mux that allows analog input from any I/O pin.

■ Crosspoint connection between any I/O pin combinations.

Note

2. 36 GPIOs = 33 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.

IDAC

Reference

Buffer

Vr

Cinternal

Cap Sense Counters

Comparator

Mux

Refs

CapSense

Clock Select

Oscillator

CSCLK

IMO

CS1

CS2

CSN

Cexternal (P0[1]

or P0[3])

[+] Feedback

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