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CY7C63743C-SXC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C63743C-SXC
Description  enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller
Download  53 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C63743C-SXC Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY7C63722C
CY7C63723C
CY7C63743C
Document #: 38-08022 Rev. *E
Page 5 of 53
MOV A,DSPINIT
Direct
“Direct” address mode is used when the data operand is a
variable stored in SRAM. In that case, the one byte address of
the variable is encoded in the instruction. As an example,
consider an instruction that loads A with the contents of memory
address location 0x10h:
MOV A, [10h]
In normal usage, variable names are assigned to variable
addresses using “EQU” statements to improve the readability of
the assembler source code. As an example, the following code
is equivalent to the example shown above.
buttons: EQU 10h
MOV A, [buttons]
Indexed
“Indexed” address mode allows the firmware to manipulate
arrays of data stored in SRAM. The address of the data operand
is the sum of a constant encoded in the instruction and the
contents of the “X” register. In normal usage, the constant will be
the “base” address of an array of data and the X register will
contain an index that indicates which element of the array is
actually addressed.
array: EQU 10h
MOV X,3
MOV A, [x+array]
This would have the effect of loading A with the fourth element
of the SRAM “array” that begins at address 0x10h. The fourth
element would be at address 0x13h.
Instruction Set Summary
Refer to the CYASM Assembler User’s Guide for detailed infor-
mation on these instructions. Note that conditional jump instruc-
tions (i.e., JC, JNC, JZ, JNZ) take five cycles if jump is taken, four
cycles if no jump.
MNEMONIC
Operand
Opcode
Cycles
MNEMONIC
Operand
Opcode
Cycles
HALT
00
7
NOP
20
4
ADD A,expr
data
01
4
INC A
acc
21
4
ADD A,[expr]
direct
02
6
INC X
x
22
4
ADD A,[X+expr]
index
03
7
INC [expr]
direct
23
7
ADC A,expr
data
04
4
INC [X+expr]
index
24
8
ADC A,[expr]
direct
05
6
DEC A
acc
25
4
ADC A,[X+expr]
index
06
7
DEC X
x
26
4
SUB A,expr
data
07
4
DEC [expr]
direct
27
7
SUB A,[expr]
direct
08
6
DEC [X+expr]
index
28
8
SUB A,[X+expr]
index
09
7
IORD expr
address
29
5
SBB A,expr
data
0A
4
IOWR expr
address
2A
5
SBB A,[expr]
direct
0B
6
POP A
2B
4
SBB A,[X+expr]
index
0C
7
POP X
2C
4
OR A,expr
data
0D
4
PUSH A
2D
5
OR A,[expr]
direct
0E
6
PUSH X
2E
5
OR A,[X+expr]
index
0F
7
SWAP A,X
2F
5
AND A,expr
data
10
4
SWAP A,DSP
30
5
AND A,[expr]
direct
11
6
MOV [expr],A
direct
31
5
AND A,[X+expr]
index
12
7
MOV [X+expr],A
index
32
6
XOR A,expr
data
13
4
OR [expr],A
direct
33
7
XOR A,[expr]
direct
14
6
OR [X+expr],A
index
34
8
XOR A,[X+expr]
index
15
7
AND [expr],A
direct
35
7
CMP A,expr
data
16
5
AND [X+expr],A
index
36
8
CMP A,[expr]
direct
17
7
XOR [expr],A
direct
37
7
CMP A,[X+expr]
index
18
8
XOR [X+expr],A
index
38
8
MOV A,expr
data
19
4
IOWX [X+expr]
index
39
6
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