Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C09179V-12AXC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C09179V-12AXC
Description  3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C09179V-12AXC Datasheet(HTML) 3 Page - Cypress Semiconductor

  CY7C09179V-12AXC Datasheet HTML 1Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 2Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 3Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 4Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 5Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 6Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 7Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 8Page - Cypress Semiconductor CY7C09179V-12AXC Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 28 page
background image
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 3 of 28
Functional Description
The CY7C09089V/99V and CY7C09179V/99V are high speed
synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port
static RAMs. Two ports are provided, permitting independent,
simultaneous access for reads and writes to any location in
memory.[4] Registers on control, address, and data lines enable
minimal setup and hold times. In pipelined output mode, data is
registered for decreased cycle time. Clock to data valid
tCD2 =6.5 ns[5] (pipelined). Flow-through mode can also be used
to bypass the pipelined output register to eliminate access
latency. In flow-through mode, data is available tCD1 = 18 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to enable the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE0 LOW and CE1 HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW-to-HIGH transition of
that port’s clock signal. This reads/writes one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and loops
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Notes
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. See page 9 and page 10 for Load Conditions.
[+] Feedback


Similar Part No. - CY7C09179V-12AXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C09179V-12AXC CYPRESS-CY7C09179V-12AXC Datasheet
535Kb / 18P
   3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
CY7C09179V-12AXC CYPRESS-CY7C09179V-12AXC Datasheet
663Kb / 28P
   3.3 V 32 K/64 K/128 K 횞 8/9 Synchronous Dual-Port Static RAM
More results

Similar Description - CY7C09179V-12AXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C09089V CYPRESS-CY7C09089V_12 Datasheet
663Kb / 28P
   3.3 V 32 K/64 K/128 K 횞 8/9 Synchronous Dual-Port Static RAM
CY7C09089V99V CYPRESS-CY7C09089V99V Datasheet
652Kb / 28P
   3.3 V 32 K/64 K/128 K 횞 8/9
CY7C0851V CYPRESS-CY7C0851V Datasheet
661Kb / 39P
   FLEx36??3.3 V 32 K / 64 K / 128 K / 256 K 횞 36 Synchronous Dual-Port RAM
CYD04S72V CYPRESS-CYD04S72V_11 Datasheet
914Kb / 30P
   FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM
CY7C09269V CYPRESS-CY7C09269V_12 Datasheet
480Kb / 22P
   3.3 V 16 K / 32 K / 64 K 횞 16 / 18 Synchronous Dual-Port Static RAM
CY7C027V CYPRESS-CY7C027V_13 Datasheet
641Kb / 24P
   3.3 V 32 K / 64 K 횞 16 / 18 Dual-Port Static RAM
CY7C09159AV CYPRESS-CY7C09159AV_11 Datasheet
434Kb / 19P
   3.3-V 8 K 횞 9 Synchronous Dual Port Static RAM
logo
MOSAIC
PUMA68S4000X-010 MOSAIC-PUMA68S4000X-010 Datasheet
119Kb / 11P
   128 K x 32 Static RAM
logo
Cypress Semiconductor
CY7C09349AV CYPRESS-CY7C09349AV_12 Datasheet
351Kb / 20P
   3.3 V 4 K/8 K 횞 18 Synchronous Dual Port Static RAM
CY7C09569V CYPRESS-CY7C09569V_12 Datasheet
688Kb / 32P
   3.3 V 16 K / 32 K 횞 36 FLEx36짰 Synchronous Dual-Port Static RAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com