CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *F

Page 6 of 22

It is not necessary to write to all the offset registers at one time.

A subset of the offset registers can be written; then by bringing

the WEN2/LD input HIGH, the FIFO is returned to normal read

and write operation. The next time WEN2/LD is brought LOW, a

write operation stores data in the next offset register in

sequence.

The contents of the offset registers can be read to the data

outputs when WEN2/LD is LOW and both REN1 and REN2 are

LOW. LOW-to-HIGH transitions of RCLK read register contents

to the data outputs. Writes and reads should not be performed

simultaneously on the offset registers.

Programmable Flag (PAE, PAF) Operation

Whether the flag offset registers are programmed as described

in Table 1 or the default values are used, the programmable

almost-empty flag (PAE) and programmable almost-full flag

(PAF) states are determined by their corresponding offset

registers and the difference between the read and write pointers.

The number formed by the empty offset least significant bit

register and empty offset most significant bit register is referred

to as n and determines the operation of PAE. PAE is synchronized to

the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW

when the FIFO contains n or fewer unread words. PAE is set

HIGH by the LOW-to-HIGH transition of RCLK when the FIFO

contains (n+1) or greater unread words.

The number formed by the full offset least significant bit register

and full offset most significant bit register is referred to as m and

determines the operation of PAF. PAF is synchronized to the

LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW

when the number of unread words in the FIFO is greater than or

equal to CY7C4261V (16k – m), CY7C4271V (32k – m),

CY7C4281V (64k – m) and CY7C4291V (128k – m). PAF is set

HIGH by the LOW-to-HIGH transition of WCLK when the number

of available memory locations is greater than m.

Table 1. Writing the Offset Registers[1]

LD

WEN

WCLK

Selection

0

0

0

1

No operation

1

0

Write into FIFO

1

1

No operation

Empty offset (LSB)



Empty offset (MSB)



Full offset (LSB)



Full offset (MSB)

Table 2. Status Flags

Number of Words in FIFO

FF PAF PAE EF

CY7C4261V

CY7C4271V

CY7C4281V

CY7C4291V

0

0

0

0

H

H

L

L

1 to n[2]

1 to n[2]

1 to n[2]

1 to n[2]

H

H

L

H

(n + 1) to (1638

 (m + 1)) (n + 1) to (32768  (m + 1)) (n + 1) to (65536  (m + 1)) (n + 1) to (131072  (m + 1))

H

H

H

H

(16384

 m)[3] to 16383 (32768  m)[3] to 32767

(65536

 m)[3] to 65535

(131072

 m)[3] to 131071

H

L

H

H

16384

32768

65536

131072

L

L

H

H

Notes

1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.

2. n = Empty Offset (n = 7 default value).

3. m = Full Offset (m = 7 default value).

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