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CY7C4291V Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY7C4291V Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 22 page CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Document #: 38-06013 Rev. *F Page 4 of 22 PLCC D1 D0 RCLK VCC GND WCLK WEN2/LD Q8 Q7 PAF PAE 5 6 7 8 9 10 11 12 13 REN1 OE REN2 4321 31 30 32 21 22 23 24 27 28 29 25 26 14 15 16 17 18 19 20 Q6 Q5 WEN1 RS Top View CY7C4261V CY7C4271V CY7C4281V CY7C4291V Pin Configuration Pin Definitions Pin No. Signal Name Description I/O Description 1–6, 30–32 D08 Data inputs I Data inputs for 9-bit bus. 1–6, 30–32 Q08 Data outputs O Data outputs for 9-bit bus. 28 WEN1 Write Enable 1 I The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. 26 WEN2/LD Dual mode pin Write Enable 2 I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Load 10, 12 REN1, REN2 Read Enable inputs I Enables the device for Read operation. Both REN1 and REN2 must be asserted to allow a read operation. 27 WCLK Write Clock I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH and the FIFO is not full. When LD is asserted, WCLK writes data into the programmable flag-offset register. 11 RCLK Read Clock I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO are not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register. 14 EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. 15 FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. 8 PAE Programmable Almost Empty O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAE is synchronized to RCLK. 7 PAF Programmable Almost Full O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is synchronized to WCLK. 29 RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power-up. 13 OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. [+] Feedback |
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