CY7C1561KV18

CY7C1576KV18

CY7C1565KV18

Document Number: 001-15878 Rev. *L

Page 8 of 29

DOFF

Input

PLL turn-off

− Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings

in the PLL turned off operation differs from those listed in this datasheet. For normal operation, this pin

can be connected to a pull-up through a 10 K

Ω or less pull-up resistor. The device behaves in QDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167

MHz with QDR I timing.

TDO

Output

Test data out (TDO) for JTAG

TCK

Input

Test clock (TCK) pin for JTAG

TDI

Input

Test data in (TDI) pin for JTAG

TMS

Input

Test mode select (TMS) pin for JTAG

NC

N/A

Not Connected to the die. Can be tied to any voltage level.

NC/144M

N/A

Not Connected to the die. Can be tied to any voltage level.

NC/288M

N/A

Not Connected to the die. Can be tied to any voltage level.

Input-

Reference

Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power Supply Power supply inputs to the core of the device

Ground

Ground for the device

Power Supply Power supply inputs for the outputs of the device

Pin Name

I/O

Pin Description

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