CY7C1518AV18

CY7C1520AV18

Document Number: 001-06982 Rev. *I

Page 9 of 29

Truth Table

The following is the truth table for parts, CY7C1518AV18 and CY7C1520AV18. [2, 3, 4, 5, 6, 7]

Operation

K

LD

R/W

DQ

DQ

Write cycle:

Load address; wait one cycle;

input write data on consecutive K and K rising edges.

L–H

L

L

D(A1) at K(t + 1)

 D(A2) at K(t + 1) 

Read cycle:

Load address; wait one and a half cycle;

read data on consecutive C and C rising edges.

L–H

L

H

Q(A1) at C(t + 1)

 Q(A2) at C(t + 2) 

NOP: No operation

L–H

H

X

High Z

High Z

Standby: Clock stopped

Stopped

X

X

Previous state

Previous state

Burst Address Table

(CY7C1518AV18, CY7C1520AV18)

First Address (External)

Second Address (Internal)

X..X0

X..X1

X..X1

X..X0

Write Cycle Descriptions

The following table represents the write cycle description for the part, CY7C1518AV18. [2, 8]

K

K

Comments

L

L

L–H

–

During the data portion of a write sequence



L

L

–

L–H During the data portion of a write sequence



L

H

L–H

–

During the data portion of a write sequence



L

H

–

L–H During the data portion of a write sequence



H

L

L–H

–

During the data portion of a write sequence



H

L

–

L–H During the data portion of a write sequence



H

H

L–H

–

No data is written into the devices during this portion of a write operation.

H

H

–

L–H No data is written into the devices during this portion of a write operation.

Notes

2. X = “Do not Care,” H = Logic HIGH, L = Logic LOW,



3. Device powers up deselected with the outputs in a tristate condition.

4. On CY7C1518AV18 and CY7C1520AV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses

sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

of a write cycle, as long as the setup and hold requirements are achieved.

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