CY7C1471BV33_11 datasheet(11/35 Pages) CYPRESS

Part #	CY7C1471BV33

Description	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

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11 / 35 page

CY7C1471BV33, CY7C1473BV33, CY7C1475BV33

Document Number: 001-15029 Rev. *E

Page 11 of 35

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are all asserted active, and (3) WE is asserted LOW.

The address presented to the address bus is loaded into the

Address Register. The Write signals are latched into the Control

Logic block. The data lines are automatically tri-stated

regardless of the state of the OE input signal. This allows the

external logic to present the data on DQs and DQPX.

On the next clock rise the data presented to DQs and DQPX (or

a subset for Byte Write operations, see section Truth Table for

Read/Write on page 13 for details), input is latched into the

device and the write is complete. Additional accesses

(read/write/deselect) can be initiated on this cycle.

The data written during the write operation is controlled by BWX

signals. The CY7C1471BV33, CY7C1473BV33, and

CY7C1475BV33 provide Byte Write capability that is described

in the section Truth Table for Read/Write on page 13. The input

WE with the selected BWX input selectively writes to only the

desired bytes. Bytes not selected during a Byte Write operation

remain unaltered. A synchronous self timed write mechanism is

provided to simplify the write operations. Byte write capability is

included to greatly simplify read/modify/write sequences, which

can be reduced to simple byte write operations.

Because the CY7C1471BV33, CY7C1473BV33, and

CY7C1475BV33 are common I/O devices, do not drive data into

the device when the outputs are active. The Output Enable (OE)

can be deasserted HIGH before presenting data to the DQs and

DQPX inputs. Doing so tri-states the output drivers. As a safety

precaution, DQs and DQPX are automatically tri-stated during

the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33

have an on-chip burst counter that enables the user to supply a

single address and conduct up to four write operations without

reasserting the address inputs. ADV/LD must be driven LOW to

load the initial address, as described in section Single Write

Accesses on page 11. When ADV/LD is driven HIGH on the

subsequent clock rise, the chip enables (CE1, CE2, and CE3)

and WE inputs are ignored and the burst counter is incremented.

Drive the correct BWX inputs in each cycle of the burst write to

write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

and the completion of the operation is not guaranteed. The

device must be deselected before entering the “sleep” mode.

CE1, CE2, and CE3, must remain inactive for the duration of

tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table

(MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD – 0.2 V

–

120

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2 V

2tCYC

–ns

tZZI

ZZ active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

–

ns

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CY7C1471BV33 Datasheet(PDF) 11 Page - Cypress Semiconductor

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