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CY7C1472BV25 Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C1472BV25 Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 29 page CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document Number: 001-15032 Rev. *I Page 10 of 29 Truth Table The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/Write Abort (Begin Burst) None L L L L H X L L-H Tri-State Write Abort (Continue Burst) Next X L H X H X L L-H Tri-State Ignore Clock Edge (Stall) Current X L X X X X H L-H – Sleep Mode None X H X X X X X X Tri-State Notes 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Partial Write Cycle Description on page 11 for details. 2. Write is defined by WE and BW[a:d]. See Partial Write Cycle Description on page 11 for details. 3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQs and DQP[a:d] = tri-state when OE is inactive or when the device is deselected, and DQs = data when OE is active. [+] Feedback |
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