CY7C1329H_11 datasheet(7/20 Pages) CYPRESS

Part #	CY7C1329H

Description	2-Mbit (64 K x 32) Pipelined Sync SRAM 2.5 V/3.3 V I/O operation

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1329H

Document #: 38-05673 Rev. *E

Page 7 of 20

Truth Table [2, 3, 4, 5, 6, 7]

Next Cycle

Address Used

CE1

CE2

CE3

ZZ

ADSP ADSC

ADV WRITE

OE

Unselected

None

H

X

L

X

L

X

Unselected

None

L

X

L

X

Unselected

None

L

X

H

L

X

Unselected

None

L

X

L

H

L

X

Unselected

None

L

X

H

L

H

L

X

Begin Read

External

None

X

H

X

Begin Read

External

L

H

L

X

L

Continue Read

L

H

L

X

H

Continue Read

L

H

L

H

L

X

L

X

Continue Read

L

H

L

H

L

X

H

L

Continue Read

L

H

L

H

L

X

H

Suspend Read

Current

X

L

H

L

H

L

Suspend Read

Current

Suspend Read

Current

X

L

H

L

H

Suspend Read

Current

X

L

X

H

L

H

L

Begin Write

Current

X

L

X

H

L

H

Begin Write

Current

X

L

H

L

X

Begin Write

External

X

L

X

H

L

X

Continue Write

X

L

H

L

Continue Write

X

L

H

Suspend Write

Current

H

X

L

X

H

L

Suspend Write

Current

H

X

L

X

H

ZZ “Sleep”

None

Current

X

L

H

L

X

Notes

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,

BWB, BWC, BWD), BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. CE1, CE2, and CE3 are available only in the TQFP package.

6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a don't care

for the remainder of the Write cycle.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

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