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CY7C1049DV33-12ZSXE Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY7C1049DV33-12ZSXE Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 14 page CY7C1049DV33 Document Number: 38-05475 Rev. *G Page 5 of 14 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions 36-pin SOJ Package 44-pin TSOP II Package Unit JA Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, two layer printed circuit board 57.91 50.66 C/W JC Thermal Resistance (Junction to Case) 36.73 17.17 C/W AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms [4] Data Retention Characteristics Over the Operating Range Parameter Description Conditions [5] Min Max Unit VDR VCC for Data Retention 2.0 – V ICCDR Data Retention Current VCC = VDR = 2.0 V, CE > VCC – 0.3 V VIN > VCC – 0.3 V or VIN < 0.3 V Industrial – 10 mA Auto – 15 mA tCDR[3] Chip Deselect to Data Retention Time 0 – ns tR[6] Operation Recovery Time tRC –ns Figure 2. Data Retention Waveform 90% 10% 3.0 V GND 90% 10% ALL INPUT PULSES * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT Rise Time: 1 V/ns Fall Time: 1 V/ns 30 pF* OUTPUT Z = 50 50 1.5 V (b) (a) 3.3 V OUTPUT 5 pF (c) R 317 R2 351 High Z characteristics: 10 ns device 3.0V 3.0V tCDR VDR > 2V DATA RETENTION MODE tR CE VCC Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 1 (c). 5. No input may exceed VCC + 0.3 V. 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. [+] Feedback |
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