CY7C1049CV33

Document #: 38-05006 Rev. *M

Page 6 of 13

AC Switching Characteristics

Over the Operating Range

Parameter [5]

Description

-8

-10

Unit

Min

Max

Min

Max

Read Cycle

[6]

100

–

100

–

s

Read cycle time

8

–

10

–ns

Address to data valid

–

8

–

10

ns

Data Hold from Address Change

3

–

3

–ns

CE LOW to data valid

–

8

–

10

ns

OE LOW to data valid

–

5

–

5ns

OE LOW to Low Z[7]

0–

0

–ns

OE HIGH to High Z[7, 8]

–4

–

5ns

CE LOW to Low Z[7]

3–

3

–ns

CE HIGH to High Z[7, 8]

–4

–

5ns

CE LOW to power up

0

–

0

–ns

CE HIGH to power down

–

8

–

10

ns

Write Cycle [9, 10]

Write cycle time

8

–

10

–ns

CE LOW to write end

6

–

7

–ns

Address setup to write end

6

–

7

–ns

Address hold from write end

0

–

0

–ns

Address setup to write start

0

–

0

–ns

WE pulse width

6

–

7

–ns

Data setup to write end

4

–

5

–ns

Data hold from write end

0

–

0

–ns

WE HIGH to Low Z[7]

3–

3

–ns

WE LOW to High Z[7, 8]

–4

–

5ns

Notes

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.

9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of

these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write.

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