CY7C199N_11 datasheet(8/14 Pages) CYPRESS

Part #	CY7C199N

Description	32 K 횞 8 Static RAM Automatic power-down when deselected

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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8 / 14 page

CY7C199N

Document #: 001-06493 Rev. *C

Page 8 of 14

Write Cycle No. 2 (CE Controlled)[17, 18, 19]

Write Cycle No. 3 (WE Controlled OE LOW)[19, 20]

Switching Waveforms (continued)

tWC

tAW

tSA

tHA

tHD

tSD

tSCE

WE

DATA I/O

ADDRESS

CE

DATA IN VALID

DATA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

CE

WE

tHZWE

DATAIN VALID

Notes

17. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms[4] on page 5. Transition is measured 500 mV from

steady-state voltage.

18. Data I/O is high impedance if OE = VIH.

19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

20. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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