CY7C185

64-Kbit (8 K × 8) Static RAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document #: 38-05043 Rev. *E

Revised April 20, 2011

Features

(300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded

DIP

Functional Description

The CY7C185[1] is a high-performance CMOS static RAM

organized as 8192 words by 8 bits. Easy memory expansion is

tri-state drivers. This device has an automatic power-down

when deselected. The CY7C185 is in a standard 300-mil-wide

DIP, SOJ, or SOIC package.

An active LOW write enable signal (WE) controls the

location addressed by the address present on the address pins

HIGH. Under these conditions, the contents of the location

addressed by the information on address pins are present on the

eight data input or output pins.

The input or output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable (WE)

is HIGH. A die coat is used to insure alpha immunity.

8K x 8

ARRAY

INPUT BUFFER

COLUMN DECODER

POWER

DOWN

WE

OE

Logic Block Diagram

Selection Guide

Description

-15

-20

-35

Maximum Access Time (ns)

15

20

35

Maximum Operating Current (mA)

130

110

100

Maximum CMOS Standby Current (mA)

15

15

15

Note

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